raulbehl / 100DaysOfRTL

100 Days of RTL
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Use of Complex Syntex #5

Closed aieask closed 2 years ago

aieask commented 2 years ago

In Day 11, I am reading design at line 43 to 44 it says,

// Valid when count greater than 0
assign valid_o = | count_ff;

What does | count_ff mean?

raulbehl commented 2 years ago

The |<sig> is the reduced-or operator in Verilog/SystemVerilog. When applied on a vector it would simply OR all of the bits of the vector together to produce a 1-bit output. Please see this link for more information

aieask commented 2 years ago

Thanks for the answer Rahul !!