Closed aieask closed 2 years ago
The |<sig>
is the reduced-or operator in Verilog/SystemVerilog. When applied on a vector it would simply OR all of the bits of the vector together to produce a 1-bit output. Please see this link for more information
Thanks for the answer Rahul !!
In Day 11, I am reading design at line 43 to 44 it says,
What does | count_ff mean?