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raulbehl / 100DaysOfRTL

100 Days of RTL
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Query with regard to simulator used for simulating the .sv files #7

Closed kevinpinto98 closed 2 years ago

kevinpinto98 commented 2 years ago

Hi @raulbehl I have a query with regard to the simulator that you are using in order to compile and simulate the system verilog files. While you have mentioned that you are using iverilog for simulation I have so far been unsuccessful in using iverilog to compile the .sv files. I have tried to look at the Makefiles as well in order to get an idea about the command syntax to compile and simulate .sv files using iverilog but unfortunately I have not been able to get any results. I would be very grateful if you could kindly guide me with regard to this issue. I am currently using EDA playground in order to compile and simulate the .sv files. But I would like to use iverilog for compilation and simulation and gtkwave for observing the waveforms.

raulbehl commented 2 years ago

Hi @kevinpinto98, Apologies for the very late reply, I've been keeping busy. Can you please help with the exact error you get when trying to run using iverilog? I haven't had any issues on simple designs and believe those should work out of the box.

raulbehl commented 2 years ago

Hi @kevinpinto98, Please let me know if you still see the problem otherwise I'd mark this as closed.

kevinpinto98 commented 2 years ago

Hi @raulbehl I am extremely sorry for the late reply. I figured out how to run the .sv files using iverilog. It seems that I was making some silly errors while running the required commands. Once again I apologize for any inconvenience caused.