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raxoft / z80test

Set of programs to test the implementation of the Zilog Z80 instruction set.
MIT License
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Updated the CRCs of `INIR->NOP'/INDR->NOP'` for z80memptr. #3

Closed redcode closed 9 months ago

redcode commented 9 months ago

I've discovered a new undocumented behavior of the inir/indr/otir/otdr instructions:

As in cpir/cpdr/ldir/lddr, when the repeat condition is met, the CPU generates an extra M-cycle of 5 T-states to decrement PC. This M-cycle performs additional flag changes, but until now it was not known that MEMPTR is also modified, being set, as in all other block instructions during this M-cycle, to PCi + 1 (PCi = value of PC at the start of the instruction, before it is incremented).

After adding this behavior to my Z80 core, z80memptr.tap fails in the following 2 steps:

102 INIR->NOP'            FAILED
CRC:F3B1BE2F   Expected:0A537B63
103 INDR->NOP'            FAILED
CRC:F3B1BE2F   Expected:0A537B63

Which matches the results obtained on real hardware by Richard Chandler, who kindly tried the test at my request on one of his machines with NEC CPU:

imagen

imagen

Of course, this "new" behavior has been tested on Visual Z80 Remix.

redcode commented 9 months ago

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raxoft commented 9 months ago

Nice find. Surprised no one noticed before, when the block instructions were scrutinized.

I'll prepare an updated release in a short time.

redcode commented 9 months ago

OK, thanks. BTW, this behaviour is confirmed on Zilog and NEC. There is no reason to think that ST CMOS will behave differently.