Simulator crashes when trying to run example 23 in VHDL

[rramunni]

I am trying to run example 23_Basic_testbench_1.0 using the VHDL code. In the Makefile, I made the folowing changes:

• Comment out VERILOG_SOURCES and uncomment VHDL_SOURCES
• SIM ?= questa
• TOPLEVEL_LANG := vhdl

I also tried with ghdl and got the same error. Using pdb I found that the line that the simulation dies on is the first await FallingEdge(dut.clk).

Using cocotb 1.8.1 and Python 3.11.5

[rramunni]

Also worth noting I was able to run example 22, the counter, in VHDL (I translated the SystemVerilog dut) without issues

[raysalemi]

Does cocotb support the Intel version of ModelSim?

[rramunni]

I had success running example 22 with questasim, which according to cocotb documentation is supported. As for Modelsim, the documentation says that VHDL FLI is not supported in PE editions.

[raysalemi]

Bummer. If FLI is not supported, then cocotb won’t work.

On Tue, Feb 6, 2024 at 4:06 PM rramunni @.***> wrote:

I had success running example 22 with questasim, which according to cocotb documentation https://docs.cocotb.org/en/stable/simulator_support.html#mentor-siemens-eda-questa is supported. As for Modelsim, the documentation says that VHDL FLI is not supported in PE editions.

— Reply to this email directly, view it on GitHub https://github.com/raysalemi/Python4RTLVerification/issues/17#issuecomment-1930750736, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAYFXWUDQD27MK2GYL4M3WLYSKLOBAVCNFSM6AAAAABC4E6WR6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSMZQG42TANZTGY . You are receiving this because you commented.Message ID: @.***>

[rramunni]

FLI is supported in questasim, though, so that isn't the issue here.

"Starting with Questa 2022.3 and cocotb 1.7 users with VHDL toplevels can choose between two communication interfaces between Questa and cocotb: the proprietary FLI and VHPI" - from the cocotb documentation

Below is the output from example 22, where I use questasim and FLI is registered and the test passes successfully.

[rramunni]

well, this was simpler than I thought... There is no clock instantiated in example 23, so it hangs and eventually dies waiting for FallingEdge(dut.clk)

@cocotb.test()
async def alu_test(dut):
    passed = True
    cvg = set()  # functional coverage
    await FallingEdge(dut.clk)

So I just added cocotb.start_soon(Clock(dut.clk, 2, units="ns").start()) the line before the await and it worked in both ghdl and questasim.

[raysalemi]

Glad I could help! 😎

[rramunni]

How do these examples work in icarus verilog without ever driving the dut clock?

[raysalemi]

I believe the Verilog drives the clock

On Thu, Feb 8, 2024 at 5:30 PM rramunni @.***> wrote:

How do these examples work in icarus verilog without ever driving the dut clock?

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