Open jeffsetter opened 5 years ago
The following generated verilog has two bugs in generation: 1) VTop does not have a clk signal (line 568 of uncorrected) 2) Invalid verilog syntax (line 48 of uncorrected) [uncorrected is "assign out = 1b'value;" ]
CoreIR json: conv_1_2_design_top.txt Uncorrected generated verilog: conv_1_2_top_uncorrected.txt Corrected verilog: conv_1_2_top.txt
Number 2 is fixed.
rdaly525
commented
5 years ago
The following generated verilog has two bugs in generation: 1) VTop does not have a clk signal (line 568 of uncorrected) 2) Invalid verilog syntax (line 48 of uncorrected) [uncorrected is "assign out = 1b'value;" ]
CoreIR json: conv_1_2_design_top.txt Uncorrected generated verilog: conv_1_2_top_uncorrected.txt Corrected verilog: conv_1_2_top.txt