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rdaly525 / coreir

BSD 3-Clause "New" or "Revised" License
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urem, srem, smod missing from coreVerilog #751

Open leonardt opened 5 years ago

leonardt commented 5 years ago

See https://github.com/rdaly525/coreir/blob/master/include/coreir/definitions/coreVerilog.hpp

These are expected based on https://github.com/StanfordAHA/Primitives/blob/master/coreirprims.csv#L9-L10

rdaly525 commented 5 years ago

@leonardt, how high of a priority is this?

leonardt commented 5 years ago

not currently blocking, this came up for fault's support for expressions. When testing the various operators, I compiled a magma circuit to match the corresponding hwtypes operator and parametrized the tests. For these test parameters, the verilog code generation fails, but for now I can just skip those tests. I don't know of anyone else who needs this.