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rdaly525 / coreir

BSD 3-Clause "New" or "Revised" License
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Zero Latency Memory #786

Open jeffsetter opened 5 years ago

jeffsetter commented 5 years ago

The memory abstraction that I would like for simulating my circuits is a memory where the read data appears at the same time as the read address comes in. Note that this might not be feasible in a normal memory, but retiming should fix this later.

Currently, coreir.mem has a cycle delay between the address being calculated and the data being provided. We should create another memory that has no latency during simulation.

rdaly525 commented 5 years ago

My intended semantics for coreir.mem was to have a 0-latency read, so this is a bug that should be fixed. I am surprised errors from this has not materialized till now.

rdaly525 commented 5 years ago

@dillonhuff, could you take a look at this bug?