This updates the verilog backend to handle the inlining of Wire primitive modules such that it preserves the intermediate wire name. Combined with https://github.com/phanrahan/magma/pull/584, this will enable users to pass through named temporary values to be generated as verilog wires. The logic is only enabled in --inline mode. It checks if we're inlining a Wire module, if so, we emit a wire named after the module instance and assign the input to the wire. We replace all references to the module outputs with the wire instance name. Finally, we use https://github.com/leonardt/verilogAST-cpp/pull/40 to prevent the inlining logic from removing the temporary wires by blacklisting the wire instance names.
This updates the verilog backend to handle the inlining of Wire primitive modules such that it preserves the intermediate wire name. Combined with https://github.com/phanrahan/magma/pull/584, this will enable users to pass through named temporary values to be generated as verilog wires. The logic is only enabled in
--inlinemode. It checks if we're inlining a Wire module, if so, we emit a wire named after the module instance and assign the input to the wire. We replace all references to the module outputs with the wire instance name. Finally, we use https://github.com/leonardt/verilogAST-cpp/pull/40 to prevent the inlining logic from removing the temporary wires by blacklisting the wire instance names.Depends on https://github.com/leonardt/verilogAST-cpp/pull/40