This is a simple pass that greedly inlines any modules which only contains a single instance.
The main purpose of this will be simplifying the clock gating inferring logic, but is also a good way to clean up some of the magma->coreIR compiler steps that do a single level of circuit wrapping.
This is a simple pass that greedly inlines any modules which only contains a single instance.
The main purpose of this will be simplifying the clock gating inferring logic, but is also a good way to clean up some of the magma->coreIR compiler steps that do a single level of circuit wrapping.