This fixes some issues in the canSel logic for hierarchical selection and removes the need for the flatten types symbol table since inline verilog is now defined inside a unique module definition/instance and the connect references are maintained in the graph. Magma is responsible for ensuring that the module interface ports are non-flattened types for now. One case is inlining a 2-d array into verilog, magma will generate n ports for each index in the 2econd dimension and insert a concat node into the verilog. This issue will be avoided when we codegenerate 2-d arrays directly (so they aren't flattened). Inlining tuples/records into verilog aren't an issue since there's no direct analog, so we only inline references to the child/leaf elements (e.g. tuple fields) so we don't have to worry about a tuple connect reference being flattened out.
This fixes some issues in the
canSellogic for hierarchical selection and removes the need for the flatten types symbol table since inline verilog is now defined inside a unique module definition/instance and the connect references are maintained in the graph. Magma is responsible for ensuring that the module interface ports are non-flattened types for now. One case is inlining a 2-d array into verilog, magma will generate n ports for each index in the 2econd dimension and insert a concat node into the verilog. This issue will be avoided when we codegenerate 2-d arrays directly (so they aren't flattened). Inlining tuples/records into verilog aren't an issue since there's no direct analog, so we only inline references to the child/leaf elements (e.g. tuple fields) so we don't have to worry about a tuple connect reference being flattened out.