Inline mantle wires from slice

[leonardt]

Fixes https://github.com/rdaly525/coreir/issues/899 Depends on https://github.com/leonardt/verilogAST-cpp/pull/53

• Adds a metadata field for enabling the inlining of a specific wire instance (by default wires are not inlined)
• Adds verilog codegen support for mantle wires (there's a subtetly where mantle wires can have "in" be an output depending on the type used in the generator)

While this avoids intermediate mantle wire instances, the mantle wire modules are still generated. I'll need to update the verilog code gen logic to figure this out, it's not necessarily easy since the module dependency graph is computed generically. We'd want to check that all instances of a module are inlined, then skip it. Not sure how blocking this is, so we can merge this with the extra unused modules code generated or wait for that improvement to be added.

[leonardt]

Turns out the mantle wire codegen issue was fairly trivial given instanceGraphNode.getInstanceList(), latest commit adds that feature.