rdaly525 / linker

Repo for the coreir linker paper
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Experiment list #3

Open rdaly525 opened 6 years ago

rdaly525 commented 6 years ago

Lets keep a list of experiments which to be able to handle, and an associated issue for each one.

We need the cross product of main is (c++,magma,verilog,Genesis,Chisel) and linked lib is (c++,magma,verilog,Genesis,Chisel)

For each of these languages, we need to know how to represent a blackbox module (header) within the language itself. Both Modules and Parameterized modules.

I think the following three blackbox modules would work great. as black boxes to link in.

//No parameters
Module adder(
  input [15:0] in0,
  input [15:0] in1,
  output [16:0] sum);

//Simple width parameter
Module #(parameter width) param_adder(
  input [width-1:0] in0,
  input [width-1:0] in1,
  output [width:0] sum);

//Parameter which changes the interface
Module #(parameter width, has_cin) param_adder(
  input [width-1:0] in0,
  input [width-1:0] in1,
  [input cin,]
  output [width:0] sum);

Index of issues

C++ is 'main' (Halide compiler for example), C++ is linked #4

C++ is 'main', magma is linked #5

C++ is 'main', verilog is linked

Magma is 'main', C++ is linked

Magma is 'main', Magma is linked

Magma is 'main', Verilog is linked #6

Verilog is 'main', magma/C++ is linked library.

Magma is 'main', Chisel is linked library Chisel is 'main', magma is linked lib (peripheral to rocketchip?)