Open der-ule opened 3 years ago
Can you please sync my repo and check if the problem is fixed?
Wow! It worked flawlessly with the latest version!
Thanks a lot once again for this magnificent software and your time and dedication!
08:06:01 A3 available
08:10:36 making pcb...
08:10:36 making board...
08:10:36 making 23 lines
08:10:36 making 4 arcs
08:10:36 making 2 polys
08:10:37 making holes...
08:10:37 pad holes: 25, skipped: 0
08:10:37 oval holes: 0
08:10:37 via holes: 117, skipped: 0
08:10:37 total holes added: 142
08:10:37 holes done
08:10:38 board done
08:10:38 making all copper layers...
08:10:38 fetch holes 'holes_wire' from cache
08:10:38 making copper layer F.Cu...
08:10:38 making pads...
08:10:43 modules: 82
08:10:43 pads: 326, skipped: 41
08:10:43 vias: 117, skipped: 0
08:10:43 total pads added: 402
08:10:59 pads done
08:10:59 making tracks...
08:10:59 making 399 tracks of width 0.20, (0/535)
08:11:03 making 136 tracks of width 0.60, (399/535)
08:11:07 tracks done
08:11:07 making zones...
08:11:07 making zone /V_SW...
08:11:07 region 1/1, holes: 0
08:11:07 making zone GND...
08:11:07 region 1/2, holes: 0
08:11:07 region 2/2, holes: 0
08:11:07 making zone GND...
08:11:07 region 1/1, holes: 0
08:11:07 making zone /V_SW...
08:11:07 region 1/1, holes: 0
08:11:07 making zone +3V3...
08:11:07 region 1/1, holes: 31
08:11:08 making zone /V_SW...
08:11:08 region 1/1, holes: 0
08:11:08 making zone "Net-(C503-Pad2)"...
08:11:08 region 1/1, holes: 0
08:11:08 making zone /VBAT+...
08:11:08 region 1/1, holes: 0
08:11:08 making zone ""...
08:11:08 making zone "Net-(C206-Pad2)"...
08:11:08 region 1/1, holes: 0
08:11:08 making zone "Net-(L203-Pad1)"...
08:11:08 region 1/1, holes: 0
08:11:08 making zone "Net-(C207-Pad2)"...
08:11:08 region 1/1, holes: 0
08:11:08 making zone "Net-(L204-Pad1)"...
08:11:08 region 1/1, holes: 0
08:11:08 making zone GND...
08:11:08 region 1/1, holes: 0
08:11:08 making zone /V_SW...
08:11:08 region 1/1, holes: 0
08:11:08 making zone "Net-(C205-Pad2)"...
08:11:09 region 1/1, holes: 0
08:11:09 making zone "Net-(C208-Pad2)"...
08:11:09 region 1/1, holes: 4
08:11:09 making zone /V_SW...
08:11:09 region 1/1, holes: 0
08:11:09 making zone "Net-(L201-Pad1)"...
08:11:09 region 1/1, holes: 0
08:11:09 making zone GND...
08:11:09 region 1/1, holes: 0
08:11:09 making zone "Net-(L202-Pad1)"...
08:11:09 region 1/1, holes: 0
08:11:09 making zone "Net-(C205-Pad2)"...
08:11:09 region 1/1, holes: 4
08:11:09 making zone /V_USB...
08:11:09 region 1/1, holes: 0
08:11:17 zones done
08:11:17 making solid
08:11:19 done solid
08:11:19 done copper layer F.Cu
08:11:19 making copper layer B.Cu...
08:11:19 making pads...
08:11:25 modules: 82
08:11:25 pads: 326, skipped: 268
08:11:25 vias: 117, skipped: 0
08:11:25 total pads added: 175
08:11:29 pads done
08:11:29 making tracks...
08:11:29 making 58 tracks of width 0.20, (0/73)
08:11:30 making 15 tracks of width 0.60, (58/73)
08:11:30 tracks done
08:11:30 making zones...
08:11:30 making zone GND...
08:11:30 region 1/1, holes: 55
08:11:40 zones done
08:11:40 making solid
08:11:42 done solid
08:11:42 done copper layer B.Cu
08:11:42 done making all copper layers
08:11:45 all done
08:14:04 making copper layer F.Cu...
08:14:04 making pads...
08:14:09 modules: 82
08:14:09 pads: 326, skipped: 41
08:14:09 vias: 117, skipped: 0
08:14:09 total pads added: 402
08:14:45 pads done
08:14:45 making tracks...
08:14:45 making 399 tracks of width 0.20, (0/535)
08:14:50 making 136 tracks of width 0.60, (399/535)
08:15:01 tracks done
08:15:01 making zones...
08:15:01 making zone /V_SW...
08:15:01 region 1/1, holes: 0
08:15:01 making zone GND...
08:15:01 region 1/2, holes: 0
08:15:01 region 2/2, holes: 0
08:15:01 making zone GND...
08:15:01 region 1/1, holes: 0
08:15:01 making zone /V_SW...
08:15:01 region 1/1, holes: 0
08:15:01 making zone +3V3...
08:15:01 region 1/1, holes: 31
08:15:02 making zone /V_SW...
08:15:02 region 1/1, holes: 0
08:15:02 making zone "Net-(C503-Pad2)"...
08:15:02 region 1/1, holes: 0
08:15:02 making zone /VBAT+...
08:15:02 region 1/1, holes: 0
08:15:03 making zone ""...
08:15:03 making zone "Net-(C206-Pad2)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(L203-Pad1)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(C207-Pad2)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(L204-Pad1)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone GND...
08:15:03 region 1/1, holes: 0
08:15:03 making zone /V_SW...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(C205-Pad2)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(C208-Pad2)"...
08:15:03 region 1/1, holes: 4
08:15:03 making zone /V_SW...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(L201-Pad1)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone GND...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(L202-Pad1)"...
08:15:03 region 1/1, holes: 0
08:15:03 making zone "Net-(C205-Pad2)"...
08:15:03 region 1/1, holes: 4
08:15:04 making zone /V_USB...
08:15:04 region 1/1, holes: 0
08:15:04 zones done
08:15:13 done copper layer F.Cu
p.s. wouldn't it be good idea to output the software version somewhere at the top when loading the plugin ? I wasn't sure if freecad picked up the changes until I saw that there was no error anymore.
p.s. wouldn't it be good idea to output the software version somewhere at the top when loading the plugin ? I wasn't sure if freecad picked up the changes until I saw that there was no error anymore.
@realthunder do you want a new ticket for this?
Hello @realthunder
I have been using your macro indirectly through the KiCAD StepUp Workbench, great stuff, thanks a bunch for it!
However, on my latest board I did notice that some zones where fused together and the space between them was not accurate, I raised the issue back at the KiCAD Forums there @easyw recommended me to raise an issue here to see if you could help.
I followed your installation instruction and loaded my board in FreeCAD using directly your plugin and the problem seems to be still there.
KiCAD![image](https://user-images.githubusercontent.com/61273032/106110614-3b48cb80-614b-11eb-8b1a-fe083c156684.png)
fcad_pcb![image](https://user-images.githubusercontent.com/61273032/106110529-22401a80-614b-11eb-8047-2b2b5a0e4778.png)
The output of the macro looks pretty normal to me:
My FreeCAD version is:
Any my KiCAD version is:
Let me know if I can somehow assist you further and once again, thank you for your time and effort!
P.S. I haven't been able to reproduce the problem with a test board, as such here is the original board with the problem: charger.zip