Closed sr-cdf closed 6 months ago
Yeah, up to now I've been either setting manually or getting from a config file. But something like this seems like a better idea
On Mon, 15 Apr 2024, 17:05 Sam Rowe, @.***> wrote:
Not a new issue, but I need to tell the system that r.adc_clk_hz = whatever every time it starts.
I've been using 2457600000 Hz, which is the ADC sample rate, divided by the interpolation factor.
I guess it would be nice to extract this from the fpga/rfdc:
r.adc_sample_rate_hz = float(r.rfdc.core.device_info['t224_sample_rate'])*1e6 r.adc_interpolation_factor = float(r.rfdc.core.device_info['t224_dt_adc0_dec_mode'].split('x')[0]) r.adc_clk_hz = r.adc_sample_rate_hz / r.adc_interpolation_factor
or using the higher level functions:
r.adc_sample_rate_hz = r.rfdc.core.get_pll_config(0,'adc')['SampleRate']*1e9
ah, there is no method to get the interpolation factor.
Not sure what the plan is here.
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Not a new issue, but I need to tell the system that
r.adc_clk_hz = whatever
every time it starts.I've been using
2457600000
Hz, which is the ADC sample rate, divided by the interpolation factor.I guess it would be nice to extract this from the fpga/rfdc:
or using the higher level functions:
Not sure what the plan is here.