Closed kassane closed 10 months ago
Entering the source code arch folder is not found RISC-V ISA. Do you want to add initial support?
Unfortunately there is no SoC that supports K extension. But it might be possible to make use of this instruction with QEMU 7.1 changelog.
Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions Extensions fully defined in the Scalar Crypto Specification: Zk, Zkn, Zks, Zkr, Zkne, Zknd, Zknh, Zksed, Zksh, Zkt Shared with the Bit-Manipulation Specification: Zbkx, Zbkc, Zbkb
Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
Extensions fully defined in the Scalar Crypto Specification: Zk, Zkn, Zks, Zkr, Zkne, Zknd, Zknh, Zksed, Zksh, Zkt
Shared with the Bit-Manipulation Specification: Zbkx, Zbkc, Zbkb
Having initial support would be great, but I don't have devices that I can use for testing.
Entering the source code arch folder is not found RISC-V ISA. Do you want to add initial support?
Unfortunately there is no SoC that supports K extension. But it might be possible to make use of this instruction with QEMU 7.1 changelog.
Reference