Open ThinkOpenly opened 4 days ago
Strings don't work well in the SMT and SystemVerilog translations, which is why we want to discourage their use.
Ideally we would have a static analysis that checks that no logic involving strings ever influences control flow. Also making things 'stringly-typed' (as per this blog post: https://www.hanselman.com/blog/stringly-typed-vs-strongly-typed) when an enum/union would be a better choice is a common beginner mistake.
The string support in the library is super bare-bones, so I think the operator is defined by the RISC-V specification.
Section "Operators" lists 15 built-in operators in a precedence table, but not their function. These should be documented, even if well known to practitioners in the art of programming.
In addition, the String type is given pretty short shrift:
(Should that text be maintained?)
However, there is at least one operator for strings which isn't even mentioned:
^
for concatenation. Or is that not in Sail proper? Or not yet? 0.18?