Internal Error for System Verilog Target

[zhanghongce]

I tried to generate System Verilog target from the RISC-V Sail model with

riscv.sv_model: $(SAIL_SRCS)
    $(SAIL) -sv $(SAIL_FLAGS) $(SAIL_SRCS) -sv_output_dir sv_output

But it reported such an error:

model/riscv_types.sail:408.21-42:
408 |     " with xlen=" ^ dec_str(sizeof(xlen)))
    |                     ^-------------------^
    | dec_str
    | 
    | Raised by primitive operation at Libsail__Reporting.err_unreachable in file "src/lib/reporting.ml", line 197, characters 18-62
    | Called from Libsail__Reporting.unreachable in file "src/lib/reporting.ml" (inlined), line 205, characters 34-61
    | Called from Jib_sv.Make.Smt.dec_str in file "src/sail_sv_backend/jib_sv.ml", line 207, characters 17-58
    | Called from Libsail__Smt_gen.Make.builtin.(fun) in file "src/lib/smt_gen.ml", line 1184, characters 21-56
    | Called from Libsail__Smt_gen.bind in file "src/lib/smt_gen.ml", line 113, characters 15-30
    | Called from Libsail__Smt_gen.fmap in file "src/lib/smt_gen.ml", line 117, characters 14-17
    | Called from Libsail__Smt_gen.bind in file "src/lib/smt_gen.ml", line 112, characters 14-17
    | Called from Libsail__Smt_gen.run in file "src/lib/smt_gen.ml", line 133, characters 14-17
    | Called from Jib_sv.Make.sv_checked_instr in file "src/sail_sv_backend/jib_sv.ml" (inlined), line 762, characters 15-49
    | Called from Jib_sv.Make.sv_fundef in file "src/sail_sv_backend/jib_sv.ml", line 792, characters 33-55
    | Called from PPrint.separate_map.(fun) in file "src/PPrint.ml", line 131, characters 21-24
    | 
    | Please report this as an issue on GitHub at https://github.com/rems-project/sail/issues

I'm new to Sail and the RISC-V model in Sail. I'm not sure if this is the issue with Sail or the model, so it is also reported in the repo for RISC-V Sail model: https://github.com/riscv/sail-riscv/issues/511

Greatly appreciate if someone can help!

[Alasdair]

We are currently in the process of a significant refactor of the SystemVerilog generation. I suspect that things will likely remain quite broken for about a month or so.

[zhanghongce]

Got it. Thanks for the info!