SV: Get RISC-V decoder through the SystemVerilog translation

The RISC-V Sail decoder is hard to generate in SystemVerilog if we try to preserve the order of every single statement, as it has a lot of guards which can read system state (like misa) to check whether certain extensions are enabled or not.

After trying a bunch of things that didn't work, this adds an attribute $[optimize_control_flow_order] which permits the Jib compilation to evaluate the expressions in control flow statements in whichever order it likes, and possibly eagerly, i.e.

if B then X else Y

can be re-written to

let y = Y in let x = X in if B then x else y

where X and Y are always evaluated.

If the function is side-effect free (as the decode is), this shouldn't change the result value, but it can change the order of side effects such as register writes or print statements.

rems-project / sail

SV: Get RISC-V decoder through the SystemVerilog translation #777

Test Results