Certain combinations of clock source and divisors, result in USB clock frequency value drift from expected theoretical value. This causes the USB device to become unrecognizable.
Example:
PLL
UCLK
240MHz
UCLK Div/5
192MHz
UCLK Div/4
Effected MCUs: RA6M1, RA6M2 and RA6M3
Workaround
There is no workaround for this issue at this time.
Issue
Effected MCUs: RA6M1, RA6M2 and RA6M3
Workaround
There is no workaround for this issue at this time.