renesas-jbrabender
commented
1 year ago @pltmcu-jci , We apologize for this warning. It is being addressed. In meantime it can be corrected by changing this line in the fsp.icf file
define block Image$$\_tz_FLASHC with alignment = \_tz_FLASH_CALIGN { section Veneer$$CMSE* };
Please note the "*" immediately after the CMSE For reference, although this warning was generated, the linker output is the same with our without the "*" (no binary change by this modification)
pltmcu-jci
Details: FSP Version: v4.4.0 Target: Renesas RA6M5 Toolchain: IAR v9.20.4.47112
Issue Description After upgrading the FSP from version 3.8.0 to version 4.4.0, I started getting a warning from my IAR project for the RA6M5 target.
Warning[Lp051]: some sections in automatic block "Veneer$$CMSE" would have been placed differently if they were not part of an automatic block. Example: section "Veneer$$CMSE (main_secure.o #71)" would have matched "section Veneer$$CMSE" at line 83 of "C:\Firmware\Auto_Repos\plt-mcu-product\product\large\carrier-test\Make\main_secure\..\..\..\..\..\ide\linker\large\main_secure_renesas.icf". Instead, it is placed in block "Veneer$$CMSE" which matched "section Veneer$$CMSE" at line 83 of "C:\Firmware\Auto_Repos\plt-mcu-product\product\large\carrier-test\Make\main_secure\..\..\..\..\..\ide\linker\large\main_secure_renesas.icf"The line 83 being referenced in the warning is
place in NSC_region { section .tz_flash_nsc_start, section Veneer$$CMSE };The
Veneer$$CMSEis defined here https://github.com/renesas/fsp/blob/master/ra/fsp/src/bsp/mcu/all/bsp_security.c#L64Note that the warning goes away if I update the line in the Linker Script to:
place in NSC_region { section .tz_flash_nsc_start, section "section Veneer$$CMSE" };