RA8 Lockup when D-Cache Enabled

[njankowski-renesas]

Issue

For RA8 devices, the Cortex-M85 may encounter a lockup condition in specific circumstances if the data cache is enabled.

This is due to Arm errata.

See errata 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 Software Developer Errata Notice (Date of issue: April 16, 2024, Document version: 14.0, Document ID: SDEN-2236668).

See the published Renesas Technical Update (TU) entitled "Limitation of D-Cache enablement" (Date: May 15, 2024, TN-RA*-A0109A/E, Rev. 1.00).

See References for links to these documents.

For FSP versions 5.0.x, 5.1.x, and 5.2.x, these errata may occur if the data cache was configured as enabled in e2 Studio in the BSP settings under BSP|Cache settings|Data cache.

The data cache is configured as disabled by default.

Workaround

For non-FSP users, follow the published Renesas Technical Update (TU) and the advice by Arm described in the errata manual.

For FSP users working with RA8 devices where data cache has been enabled, do one of the following.

1. Use version 5.3.x or newer, which applies the workarounds advised by Arm.
2. Alternatively, apply a manual patch to the R_BSP_WarmStart() function which always sets MSCR.FORCEWT and ACTLR_S[16] in the BSP_WARM_START_RESET event. For e2 Studio, this function is always created under the src/hal_entry.c source file when a new project is made. See References for links to the BSP documentation.

The workaround to be applied by a Flat or Secure application is as follows. A Non-secure application cannot apply this workaround for itself.

MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
__DSB();
__ISB();
ICB->ACTLR |= (1U << 16U);
__DSB();
__ISB();

References

1. Limitation of D-Cache enablement
2. Cortex-M85 AT640 and Cortex-M85 with FPU AT641 Software Developer Errata Notice (v14.0)
3. RA Flexible Software Package Documentation, BSP Weak Symbols
4. RA Flexible Software Package Documentation, Warm Start Callbacks