FSP5.4 RA8D1 LIN BUG with uart TX idle state low

[FloHomi]

Hi, I discovered a bug in the LIN Library of the FSP 5.4 The Idle state of the Uart TX is low, but should be hight. There are missing bits in the CCR2 Reg inside r_sci_b_lin.c see picture for blue line fix:

[renesas-abigail]

Hello @FloHomi,

The reason for the low level is that an external pull up resistor is required on TXD for sci_b_lin.

While basic LIN communication may seem to work after setting the bits you mentioned, other features of the SCI LIN, including bus conflict detection, will not work correctly. This is because SPB2DT may be used in Asynchronous mode and Manchester modes only. Operation in other modes (including Simple LIN mode, which is what sci_b_lin uses) is not guaranteed.

If you have any further questions, feel free to ask.

Abigail

References:

• 'Pin Configuration' section of the SCI_B_LIN Usage Notes
• Note 1 on SPB2DT in the section "CCR1 : Common Control Register 1" of the RA8D1 User's Manual