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rggen
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rggen
Code generation tool for control and status registers
MIT License
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Allow to specify configuration parameters on register map files
#221
taichi-ishitani
opened
2 months ago
0
Report error when unknown field is given
#220
taichi-ishitani
closed
2 months ago
0
Add variable placeholders for comments
#219
SzymonHitachi
opened
2 months ago
6
Setting protocol in the register map file has not effect and there is no warning/error
#218
m-kru
closed
2 months ago
1
rggen-vhdl generates APB interface when the protocol is specified as wishbone
#216
m-kru
closed
2 months ago
15
update workflow due to updating gemfile structure
#212
taichi-ishitani
closed
3 months ago
1
[Bug] NoMethodError is raised when loading XLSX spreadsheet
#211
taichi-ishitani
closed
3 months ago
1
XLSX input error description row/column off by one
#210
SzymonHitachi
closed
3 months ago
1
DSim cannot compile generated VHDL
#208
taichi-ishitani
closed
4 months ago
2
[bug] external register type seems to not be working
#207
SzymonHitachi
closed
4 months ago
4
Allow to specify runtime options by using config file
#205
taichi-ishitani
opened
4 months ago
0
PyUVM support
#203
taichi-ishitani
opened
5 months ago
0
Support Pkl format
#202
taichi-ishitani
opened
5 months ago
1
Parameterized bit field with
#201
taichi-ishitani
opened
6 months ago
0
Veryl support
#199
taichi-ishitani
opened
6 months ago
0
rc, w0c, w1c, wc, woc: bit field set when it should be cleared?
#198
ifkato
closed
7 months ago
3
[VHDL] Type mismatch error for an array register with offset address 0x0
#197
taichi-ishitani
closed
7 months ago
1
[Request] Add support for library name
#196
SzymonHitachi
closed
7 months ago
15
[VHDL] Array port
#195
taichi-ishitani
opened
7 months ago
0
Specify reset domain
#193
taichi-ishitani
opened
7 months ago
0
Bump codecov/codecov-action from 3 to 4
#192
dependabot[bot]
closed
8 months ago
1
backdoor read has no side effect
#191
taichi-ishitani
closed
8 months ago
1
Implement: Parameter-Driven Bit width assignment in SV/Verilog files from input file formats
#190
pratheekjain
closed
8 months ago
4
drop xls support
#189
taichi-ishitani
closed
8 months ago
1
Drop XLS support
#188
taichi-ishitani
closed
8 months ago
0
Cannot load ODS file including multi-line cell correctly
#187
taichi-ishitani
closed
8 months ago
0
Update copyright year
#186
taichi-ishitani
closed
8 months ago
0
Change loader priority
#185
taichi-ishitani
closed
8 months ago
0
Redefine rws bit field type
#184
taichi-ishitani
closed
8 months ago
0
YAML specification for custom bit type does not seem to match documentation
#183
vermea
closed
8 months ago
1
Generate IP-XACT
#182
taichi-ishitani
opened
8 months ago
0
Update spreadbase gem
#181
taichi-ishitani
closed
9 months ago
0
Update option description
#180
taichi-ishitani
closed
9 months ago
1
stop using sonarcloud
#179
taichi-ishitani
closed
9 months ago
1
Stop using sonarcloud
#178
taichi-ishitani
closed
9 months ago
0
add Ruby 3.3 support
#177
taichi-ishitani
closed
9 months ago
2
REGISTER_INDEX
#176
haridevang
closed
9 months ago
2
drop Ruby 2.7
#175
taichi-ishitani
closed
9 months ago
2
update development gems
#174
taichi-ishitani
closed
9 months ago
2
Add Ruby 3.3 support and drop Ruby 2.7 support
#173
taichi-ishitani
closed
9 months ago
0
Update development gems
#172
taichi-ishitani
closed
9 months ago
0
Add method to check if the given component is defined
#171
taichi-ishitani
closed
9 months ago
0
Modify existing features
#170
taichi-ishitani
closed
9 months ago
0
Error while starting the uvm_reg_mem_hdl_paths_seq.
#169
Tejoyadav
closed
10 months ago
4
Cannot load default plugins when newer RgGen is installed
#168
taichi-ishitani
closed
11 months ago
1
Provide Python bindings
#167
hpretl
opened
1 year ago
1
Support SPI as bus interface
#166
hpretl
opened
1 year ago
7
Bump codecov/codecov-action from 3 to 4
#165
dependabot[bot]
closed
1 year ago
0
Change protocol definition of rggen_register_if
#164
taichi-ishitani
closed
1 year ago
0
separating HW and SW access
#163
imerkado91
closed
1 year ago
2
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