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rggen / rggen-verilog-rtl

Common Verilog RTL modules for RgGen
https://github.com/rggen/rggen
MIT License
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module rggen_axi4lite_adapter verilog syntax error~ #2

Closed 275244143 closed 3 years ago

275244143 commented 3 years ago

parameter [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, parameter [BUS_WIDTH-1:0] DEFAULT_READ_DATA = '0, change to : parameter [ADDRESS_WIDTH-1:0] BASE_ADDRESS = {(ADDRESS_WIDTH){1'b0}}, parameter [BUS_WIDTH-1:0] DEFAULT_READ_DATA = {(BUS_WIDTH){1'b0}},

actual_id_width() change to: parameter ACTUAL_ID_WIDTH = (ID_WIDTH == 0) ? 1 : ID_WIDTH delete: function actual_id_width(); r_state: Signal has multiple driving blocks with different clocking: 'rggen_axi4lite_adapter.r_state' rggen_axi4lite_adapter.v:231:13: ... Location of first driving block 231 | r_state <= WAIT_FOR_RESPONSE_ACK; | ^~~ rggen_axi4lite_adapter.v:106:7: ... Location of other driving block 106 | r_state <= w_bus_strobe; | ^~~

taichi-ishitani commented 3 years ago

Hi @275244143 , Thank you for reporting this error! I will fix it.

taichi-ishitani commented 3 years ago

@275244143 ,

I've fixed these errors on fix_2 branch. Can you get the latest RLT from the above branch and check whether or not errors which you found are fixed?