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rggen / rggen-verilog-rtl

Common Verilog RTL modules for RgGen
https://github.com/rggen/rggen
MIT License
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Parameter pin not found: 'VALID_BITS' #6

Closed aignacio closed 2 years ago

aignacio commented 2 years ago

Hey @taichi-ishitani,

I'm using the Verilog plugin with rggen and I am having the following error with the generated rtl + this repository:

INFO     cocotb:simulator.py:302 %Error: /csr_out/csr_dma.v:122:8: Parameter pin not found: 'VALID_BITS'
INFO     cocotb:simulator.py:302   122 |       .VALID_BITS     (32'h00000003),
INFO     cocotb:simulator.py:302       |        ^~~~~~~~~~
INFO     cocotb:simulator.py:302 %Error: /csr_out/csr_dma.v:215:8: Parameter pin not found: 'VALID_BITS'
....

The module rggen_default_register does not have the VALID_BITS parameter. Is there another repository with the updated module to fix this compilation error? I used the following cmd to generate the csr_dma.v registers.

rggen --plugin rggen-verilog -c config.yml -o csr_out csr_dma.xlsx
taichi-ishitani commented 2 years ago

Hi @aignacio , The latest Verilog modules support the latest Verilog plugin but I have not yet released it. Can you use the previous Verilog modules 87e31da5397f4ed5cfcb282a4112124b88cd4ee5 for now?

aignacio commented 2 years ago

sure, switching now, tks for quick reply =)

taichi-ishitani commented 2 years ago

Hi @aignacio ,

I've released the latest Verilog plugin v0.4.1. https://rubygems.org/gems/rggen-verilog/versions/0.4.1

This version supports the latest common Verilog modules and the compile error which you saw is fixed.

aignacio commented 2 years ago

Thanks @taichi-ishitani !