Closed wimille closed 5 years ago
Apologies for the delay, is this still an issue? When you say VHDL mode do you mean when using the stutter mode feature, or just when using the extension in general?
Hi, Yes it's still an issue. When i say VHDL mode, i mean that i work on a VHDL file and so your plugin is active. Here's a GIF to show you a better view on this issue: https://gph.is/g/EGRNlLd
It's not clear what you are referring to, as I can see similar behaviour on both lines and cannot determine what completion you are expecting to see. Any completions with the 'abc' icon are text matches that VSCode has extracted from the document; signal names are not provided by this extension.
No both line are not similar. On the first one when i type "bar", vscode doen't suggest me signal starts with 'bar'. On the second line, vscode suggests me signals start with 'bar'. Moreover i've been the same type of test with a verilog file, and so with another extension, and i've not this type of issue.
As I said before, those completions are not provided by this extension. Having looked at the Language Configuration Guide, I can specify a regex to extract valid symbol names, but this does not explain the behaviour you are claiming. I will open a separate issue to implement the word pattern, but leave this issue closed as I cannot see how it is related to this extension.
Can you post your editor settings for showing suggestions? Default settings do not match what is in your gif and I'm wondering if that is why I haven't seen it.
You want both my settings and default editor settings ?
Settings that differ from the default please, and also your version number of VSCode.
Should be fixed in v1.0.3.
Great job! I've made a few test and, for now, all seems to work fine. My signals are suggested by vscode even after a logical operator.
Thank you.
No problem.
Hi,
It seems there is a bug in interaction between VHDL mode and autocompletion feature of vscode. As soon as i use a boolean operator such as 'and', 'or, etc, autocompletion stops to work.
For exmple if i write:
if foo = '0' and b..
All existing signals start with 'b' are not displayed as it should be.
Regards