Process inside architecture block incorrectly indented

richjyoung / vscode-modern-vhdl

Modern VSCode VHDL Support

MIT License

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Process inside architecture block incorrectly indented #35

Closed benjaminmordaunt closed 3 years ago

benjaminmordaunt commented 3 years ago

architecture A of x is
    signal sig : std_logic;
begin
    process(sig)
    begin -- <-- When finished typing begin, it jumps to a 0 indentation level.
    -- ...
end A;

richjyoung commented 3 years ago

I just tested this with the latest changes, and I think it's been resolved. Let me know if not and I will reopen.