Open Philippe91 opened 4 months ago
yes I haven't optimized for ARM. Ideally there should only be single dmb barrier.
On Sun, Mar 3, 2024 at 4:45 AM Philippe91 @.***> wrote:
Both for enqueing and dequeing, why not using compare_exchange_weak / std::memory_order_relaxed (instead of compare_exchange_strong / memory_order_seq_cst) like in Dmitry Vyukov latest implementation (2021)? This seems to make sense, as we are in a loop.
https://drive.google.com/file/d/1uCefvM3bTnWLFrcYoMxCOKGjWwHJQM2n/view
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Both for enqueing and dequeing, why not using
compare_exchange_weak / std::memory_order_relaxed
(instead ofcompare_exchange_strong / memory_order_seq_cst
) like in Dmitry Vyukov latest implementation (2021)? This seems to make sense, as we are in a loop.https://drive.google.com/file/d/1uCefvM3bTnWLFrcYoMxCOKGjWwHJQM2n/view