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risclite / R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Apache License 2.0
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I/O ports are not mapped #2

Closed jotego closed 5 years ago

jotego commented 5 years ago

I/O ports of 8051 microcontroller are not mapped at the top level instace. Is there a wrapper for this?

risclite commented 5 years ago

Hi, I do not mean to design approximation of a real 8051 MCU. Actually, I do not know exactly P0/1 ports, timers or UARTs, which are necessory of an 8051MCU. I simplify Intel8051/2 as a RISC architecture, just like ARM or RISCV.

R8051 is a processor which will transform instructions to memory operations. If you connect it with different RAMs or perpherals, R8051 will operate them according to instuctions. Maybe C/assembly code is buit based on a real 8051 MCU, however It is not necessory to have all its perpherals if you do not need a timer or UART, etc.

Just instantiate R8051 as a controller and build code from C/assembly development tools. Your code will only deal with your own RAM and perpherals, which has their own address.

I will not intend to build R8051 to be a traditional 8051 core.

jotego commented 5 years ago

Ok. Thank you for clarifying this.