Zvfh/Zvfhmin SAIL

[jjscheel]

Technical Group

Unprivileged Spec IC

ratification-pkg

Zvfh/Zvfhmin

Technical Liaison

Andrew Waterman

Task Category

SAIL model

Task Sub Category

• [ ] gcc
• [ ] binutils
• [ ] gdb
• [ ] intrinsics
• [ ] Java
• [ ] KVM
• [ ] ld
• [ ] llvm
• [ ] Linux kernel
• [ ] QEMU
• [ ] Spike

Ratification Target

2Q2023

Statement of Work (SOW)

Component names: SAIL model for Zvfh and Zvfhmin

Requirements: Extend the base vector support in RISC-V SAIL model to include support for the new Zvfh and Zvfhmin extensions

Deliverables:

• Functional SAIL implementation

Acceptance Criteria:

• Basic tests for the instructions pass
• PR for SAIL submitted and merged

Projected timeframe: (best guess date)

SOW Signoffs:

• Task group liaison sign-off
• Development partner sign-off
• Golden Model sign-off

Waiver

• [X] Freeze
• [X] Ratification

Pull Request Details

No response

[jjscheel]

Need to find someone to help me complete the SOW content.

[jjscheel]

@billmcspadden-riscv, would you kindly review my SOW text in the first entry of this issue and let me know where it can or should be improved? THANKS!

[billmcspadden-riscv]

1. Add pointers to the spec. A pointer to the github repo that holds the spec(s) would be best.
2. In either this SOW or the ACT SOW, something needs to be said about the additions to the RISCV-Config structure that might be needed for these extensions. The statement may be: "No configuration is needed for this extension." This might include a Signoff item for the RISCV Config people.
3. I think a list of configuration parameters for the model should be included. The TG should provide this list.
4. More specifically, the extension names "Zvfhmin" and "Zvfh" will need to be supported when parsing the ISA string, which will enable/disable the feature in the model.

I think most of the work for these extensions will center on configurability. There is not much (any?) new functional code that will need to be added.

[jjscheel]

Hi, @xiwang-x. I'm assigning this item to @XinlaiWan to start the discussion about whether RIOS can begin working on this now that Vector SAIL is slowing down. Please review this item and put your thoughts into this issue.

[XinlaiWan]

Hi Jeff, we'll follow the progress of this, and the development tasks will be assigned to my RIOS colleagues.

[jjscheel]

Thanks, @XinlaiWan. For clarity, these extensions have already been ratified with a waiver. As such, work can begin at any time.

Please let me know who will be working on this so that myself and @billmcspadden-riscv can be of assistance with the process.

[XinlaiWan]

Hi Jeff and Bill, my RIOS colleague, Jia'ao Li @LiGaOg will work on Zvfh/Zvfhmin Sail.

[jjscheel]

@XinlaiWan, thanks for the good news!

@LiGaOg, welcome. Please ensure you get Groups.IO profile by sending an email from your RIOS account to info@riscv.org and asking for a profile to the RISC-V Portal. After that's configured, I can ensure you get access to the proper places. Xinlai has done this so he should be able to help. Feel free to ask questions or send me an email if needed.

[LiGaOg]

@jjscheel Hi Jeff, I have sent the email and got the profile to RISC-V Portal. My RIOS email is lijiaao@rioslab.org.

[jjscheel]

Thanks, @LiGaOg. I've sent you an invite to the devpartners team in GH. Please check the riscv-admin organization for this invite.

I've also added you to several groups in Groups.IO. These will help you track other work going on in SAIL and ACT.

For this work, please ready the information in the first entry (description) of this issue, read the spec here, and ask your questions here. @billmcspadden-riscv is our resident SAIL expert and a great resource. I will find us a technical resource to answer questions about this which stump Bill.

Please reach out to me if you have any questions.

[jjscheel]

@LiGaOg, have you had a chance to look at this yet? If so, can you provide any status on how it is going?

[LiGaOg]

@jjscheel OK, i have just finished hacking the source code of my part (sail vector part and other relevant source code). I'm planning to move Zvfh/Zvfhmin part of the whole sail vector as individual parts.

[jjscheel]

@LiGaOg, how is this work coming along? Can you report any progress for me, please?

[LiGaOg]

@jjscheel Terribly sorry for being so late, I got tons of work to do in recent months 😭. I have completed the sail code for Zvfhmin part. I use some small self-written tests to test Zvfhmin SAIL. Currently working on some detailed tests.

[jjscheel]

Thank you, @LiGaOg. That is very good news! Usually, "no news" is "bad news". Please keep up the great work.

If you have any questions about your Sail, please reach out to @billmcspadden-riscv. And, if you don't mind posting an update every couple weeks, that will save me from bugging you. :-D

[LiGaOg]

@jjscheel Okay, Jeff, after the Chinese New Year holiday, I'll report back on all the work I've done in the last period, and I apologize for the lack of news, as there's been too much to focus on in recent months T_T, and I'll make sure to report back on progress every few weeks.

[jjscheel]

No worries. Happy New Year!

[LiGaOg]

Hi jeff @jjscheel . I have completed the very basic version of Zvfhmin. For Zvfhmin, it only supports instructions for conversion between f16 and f32/f64. So for all the relevant utils functions in riscv_insts_vext_utils.sail and riscv_insts_vext_fp.sail (like fp_add). If the width of the vector floating-point element (SEW) is 16, it will trigger an illegal instruction exception (In my implementation, I use handle_illlegal()).

As for Zvfh, I'm a little confused about the dependencies of those extensions.

• The first question is, SAIL has already implemented Zvfh (half-precision fp arithmetic is supported). So my task is to make Zvfh decoupled from the original version (providing options to build a model without half-precision fp, with Zvfhmin, and with Zvfh).
• The second question is, is Zvfhmin/Zvfh has relations to Zfhmin/Zfh? For example, if the floating-point extension doesn't support Zfhmin/Zfh, is it right for the vector extension to support Zvfh/Zvfhmin?

[jjscheel]

@billmcspadden-riscv, can you help with Lijiaao's questions? If you cannot, let me know and we can engage someone from Unpriv IC.

[jjscheel]

@LiGaOg, per the text in the ratified version of Zvfh/Zvfhmin, I see this answer to your second question ("The second question is, is Zvfhmin/Zvfh has relations to Zfhmin/Zfh?"):

The Zvfhmin extension depends on the Zve32f extension.

The Zvfh extension depends on the Zve32f and Zfhmin extensions.

Do these statements answer your questions?

[jjscheel]

@LiGaOg, did my explanation make sense about the second question in your list?

The Zvfhmin extension depends on the Zve32f extension.

The Zvfh extension depends on the Zve32f and Zfhmin extensions.

[LiGaOg]

Currently I'm not working in RIOS Lab, my new colleague will work on this issue. I have transferred my work to him. He'll be here soon to take over the job.

[jjscheel]

Thanks, @LiGaOg. Please provide info for colleague.

[jjscheel]

@LiGaOg, any news on who will be picking up this work?

[jjscheel]

@Oxyw, thanks for agreeing to look into who is going to replace LiGaOg.

[Oxyw]

Hi, @jjscheel. This is my new colleague, Wenyu Huang @wwwwwwOwO. She will be taking over this work.

[jjscheel]

Hellow Wenyu @wwwwwwOwO. Please drop me an email at jeff@riscv.org so that we can exchange some information so that you can participate. I'm happy to hear that you're willing to help!!!

[wwwwwwOwO]

Hi Jeff, I’m Wenyu^ - ^. I’ve sent an email to you, my email address is wenyu.huang@rioslab.org

[jjscheel]

@wwwwwwOwO, now assigned. Thanks!