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Sail Softfloat Replacement #40

Open jjscheel opened 5 months ago

jjscheel commented 5 months ago

Technical Group

Applications & Tools HC

ratification-pkg

Technical Debt

Technical Liaison

Bill McSpadden

Task Category

Sail

Task Sub Category

Ratification Target

3Q2023

Statement of Work (SOW)

Component names: Sail

Requirements: In the RISC-V Sail model, floating point operations are implemented (executed) using the Berkley SoftFloat package (written by John Hauser). See: https://github.com/riscv/sail-riscv/tree/master/c_emulator/SoftFloat-3e This code is written in C in roughly 320 files and 37K lines of code. (Note: some of this work has already been done in support of Vector Crypto by Charalampos Mitrodimas.)

The functionality in SoftFloat needs to be replicated in native Sail code. The primary purpose of this project is to provide a native Sail description of floating point operations which can be used as the canonical definition of FP ops for RISC-V. This Sail code can be imported into the RISC-V ISA documentation.

The API interface for floating point ops must remain the same.

Deliverables:

  1. Set of Sail files that fully implement the functionality of SoftFloat. The code will live in the RISC-V Sail (golden model) repository.

Acceptance Criteria:

  1. Approved PR to the Sail community for all code.
  2. ACT test results equivalency between new and Softfloat (prior) code bases.

Projected timeframe: (best guess date) 6 person months

SOW Signoffs: (delete those not needed)

Waiver

Pull Request Details

Incarnation-p-lee commented 5 months ago

Thank @jjscheel for the clear description of this task.

Hi @billmcspadden-riscv

Just went through the SoftFloat, and would like to double-check if my understanding is correct before any further actions.

Currently, the sail-riscv c_emulator has riscv_softfloat.c, which leverages the SoftFloat library/package. For example, the function softfloat_f64roundToInt depends on the f64_roundToInt (implemented in SoftFloat-3e/source/f64_roundToInt.c). And we need to migrate the c-implemented code to the sail (aka ./model as I understand). Then the e_emulator can leverage the generated code (by sail model) instead of the SoftFloat library/package.

Unfortunately, my previous experience almost focuses on c, java, c#, and of course the green hand for sail. Could you please help to share some guide or something like that as above mentioned that part of works has done for supporting RVV Crypto. I think I need to try some POC by myself first, and then evaluate the efforts, as well as the plan for the task.

CC @haicheng-li

Incarnation-p-lee commented 5 months ago

Table of contents

I summarize what I have learned about the softfloat as below and possible work items. Could you please help to double-check if everything is correct? Then we can start the work step by step.

What we have

The riscv insn sail models treat the model/riscv_softfloat_interface.sail as the contract of how to leverage the softfloat externally. Like in c_emulator. For example, the sail function riscv_f32Eq in the model/riscv_softfloat_interface.sail will call externally to the function softfloat_f32eq in c_emulator/riscv_softfloat.c.

graph LR
  subgraph The C Emulator
    B1[softfloat]
  end

  subgraph Sail Models
    A1[riscv-insn-fp-*] --depends on--> A2[riscv_software_interface] --external call--> B1
  end

What we would like to do

AFAIK, we would like to get rid of the c_mulator/riscv_softfloat, and implement the softfloat in the sail language. And then eliminate the c_emulator/softfloat in this repo.

graph LR
  subgraph The C Emulator
    B1[softfloat]
  end

  subgraph Sail Models
    A1[riscv-insn-fp-*] --depends on--> A2[riscv_software_interface] --call--> A3[softfloat in sail]
    A2 x--external call--x B1
  end

How we land

For safe consideration, I may suggest we still treat the model/riscv_softfloat_interface.sai as the contract, and only replace the external call to c_emulator/software one by one. For example:

// val     extern_f32Eq = {c: "softfloat_f32eq", ocaml: "Softfloat.f32_eq", lem: "softfloat_f32_eq"} : (bits_S, bits_S) -> unit                                                                                                             val      riscv_softfloat_f32_eq : (bits_S, bits_S) -> unit
val      riscv_f32Eq : (bits_S, bits_S) -> (bits_fflags, bool)
function riscv_f32Eq (v1, v2) = {
  riscv_softfloat_f32_eq(v1, v2);
  // extern_f32Eq(v1, v2);
  (float_fflags[4 .. 0], bit_to_bool(float_result[0]))
}

Then we only need to implement the sail function riscv_softfloat_f32_eq somewhere else and limit the risk to the existing sail modes. For example, I may suggest we take the below arrangement. And we can even parallel the implementation under softfloat folder once stable. Finally, it looks like we may not need implement everything of e_emulator/software up to a point.

model/
├── README.md
├── riscv_softfloat_interface.sail
└── float
    ├── riscv_float_eq.sail
    ├── riscv_float_lt.sail
    └── riscv_float_gt.sail

Sail Function to be Implemented

According to the API defined in riscv_software_interface, at least we have below sail function to be implemented.

Not start

Under Review

Completed

Issues

CC @haicheng-li for awareness.

billmcspadden-riscv commented 5 months ago

Side comment: Because this is such a large change to the code, we don't want to have a large PR to review. Please consider how you might subdivide the problem such that we only have to review 1000-2000 lines of code at a time.

Bill Mc.

On Tue, Feb 6, 2024 at 3:15 AM Pan Li @.***> wrote:

I summarize what I have learned about the softfloat as below and possible work items. Could you please help to double-check if everything is correct? Then we can start the work step by step. What we have

The riscv insn sail models treat the model/riscv_softfloat_interface.sail as the contract of how to leverage the softfloat externally. Like in c_emulator. For example, the sail function riscv_f32Eq in the model/riscv_softfloat_interface.sail will call externally to the function softfloat_f32eq in c_emulator/riscv_softfloat.c.

graph LR subgraph The C Emulator B1[softfloat] end

subgraph Sail Models A1[riscv-insn-fp-*] --depends on--> A2[riscv_software_interface] --extern call--> B1 end

What we would like to do

AFAIK, we would like to get rid of the c_mulator/riscv_softfloat, and implement the softfloat in the sail language. And then eliminate the c_emulator/softfloat in this repo.

graph LR subgraph The C Emulator B1[softfloat] end

subgraph Sail Models A1[riscv-insn-fp-*] --depends on--> A2[riscv_software_interface] --call--> A3[softfloat in sail] A2 x--external call--x B1 end

How we land

For safe consideration, I may suggest we still treat the model/riscv_softfloat_interface.sai as the contract, and only replace the external call to c_emulator/software one by one. For example:

// val extern_f32Eq = {c: "softfloat_f32eq", ocaml: "Softfloat.f32_eq", lem: "softfloat_f32_eq"} : (bits_S, bits_S) -> unit val riscv_softfloat_f32_eq : (bits_S, bits_S) -> unit val riscv_f32Eq : (bits_S, bits_S) -> (bits_fflags, bool) function riscv_f32Eq (v1, v2) = { riscv_softfloat_f32_eq(v1, v2); // extern_f32Eq(v1, v2); (float_fflags[4 .. 0], bit_to_bool(float_result[0])) }

Then we only need to implement the sail function riscv_softfloat_f32_eq somewhere else and limit the risk to the existing sail modes. For example, I may suggest we take the below arrangement. And we can even parallel the implementation under softfloat folder once stable. Finally, it looks like we may not need implement everything of e_emulator/software up to a point.

model/ ├── README.md ├── riscv_softfloat_interface.sail └── softfloat ├── riscv_softfloat_eq.sail ├── riscv_softfloat_lt.sail └── riscv_softfloat_gt.sail

Sail Function to be Implemented

According to the API defined in riscv_software_interface, at least we have below sail function to be implemented.

  • riscv_f16Add
  • riscv_f16Sub
  • riscv_f16Mul
  • riscv_f16Div
  • riscv_f32Add
  • riscv_f32Sub
  • riscv_f32Mul
  • riscv_f32Div
  • riscv_f64Add
  • riscv_f64Sub
  • riscv_f64Mul
  • riscv_f64Div
  • riscv_f16MulAdd
  • riscv_f32MulAdd
  • riscv_f64MulAdd
  • riscv_f16Sqrt
  • riscv_f32Sqrt
  • riscv_f64Sqrt
  • riscv_f16ToI32
  • riscv_f16ToUi32
  • riscv_i32ToF16
  • riscv_ui32ToF16
  • riscv_f16ToI64
  • riscv_f16ToUi64
  • riscv_i64ToF16
  • riscv_ui64ToF16
  • riscv_f32ToI32
  • riscv_f32ToUi32
  • riscv_i32ToF32
  • riscv_ui32ToF32
  • riscv_f32ToI64
  • riscv_f32ToUi64
  • riscv_i64ToF32
  • riscv_ui64ToF32
  • riscv_f64ToI32
  • riscv_f64ToUi32
  • riscv_i32ToF64
  • riscv_ui32ToF64
  • riscv_f64ToI64
  • riscv_f64ToUi64
  • riscv_i64ToF64
  • riscv_ui64ToF64
  • riscv_f16ToF32
  • riscv_f16ToF64
  • riscv_f32ToF64
  • riscv_f32ToF16
  • riscv_f64ToF16
  • riscv_f64ToF32
  • riscv_f16Lt
  • riscv_f16Lt_quiet
  • riscv_f16Le
  • riscv_f16Le_quiet
  • riscv_f16Eq
  • riscv_f32Lt
  • riscv_f32Lt_quiet
  • riscv_f32Le
  • riscv_f32Le_quiet
  • riscv_f32Eq
  • riscv_f64Lt
  • riscv_f64Lt_quiet
  • riscv_f64Le
  • riscv_f64Le_quiet
  • riscv_f64Eq
  • riscv_f16roundToInt
  • riscv_f32roundToInt
  • riscv_f64roundToIn

Issues

I am working on one POC of a simple API like f32eq, and there are some global variables like floating control and status flags .. etc, will keep you all posted.

CC @haicheng-li https://github.com/haicheng-li for awareness.

— Reply to this email directly, view it on GitHub https://github.com/riscv-admin/dev-partners/issues/40#issuecomment-1929301307, or unsubscribe https://github.com/notifications/unsubscribe-auth/AXROLOBBJI7DAEHKNTYW3ODYSIGF3AVCNFSM6AAAAABCRDLEGSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSMRZGMYDCMZQG4 . You are receiving this because you were mentioned.Message ID: @.***>

-- Bill McSpadden Formal Verification Engineer RISC-V International mobile: 503-807-9309

Incarnation-p-lee commented 5 months ago

Sure thing, actually I may prefer 200-300(excludes test code) lines per PR for review. By the way, does sail-riscv repo take Merge or Squash Merge for PR?

Incarnation-p-lee commented 4 months ago

Status Update Mar 4, 2024

Incarnation-p-lee commented 4 months ago

Thanks @jjscheel for the SOW description. ACK the SOW from my side.

To clarify, please feel free to comment if any concerns or questions about below open issue.

billmcspadden-riscv commented 4 months ago

Hi Pan.

Would you please explain a bit more about "more support required from the sail compiler". As I understand it, TestFloat is a set of tests for checking the implementation of a binary floating point library. How does this have anything to do with the Sail compiler?

Bill Mc.

On Tue, Mar 5, 2024 at 5:41 PM Pan Li @.***> wrote:

Thanks @jjscheel https://github.com/jjscheel for the SOW description. ACK the SOW from my side.

To clarify, please feel free to comment if any concerns or questions about below open issue.

  • The softfloat_3e_test http://www.jhauser.us/arithmetic/TestFloat.html porting to sail-riscv is NOT in the scope of this SOW due to some more support required from the sail compiler. If so I think we need to record it by a task somewhere.

— Reply to this email directly, view it on GitHub https://github.com/riscv-admin/dev-partners/issues/40#issuecomment-1979925781, or unsubscribe https://github.com/notifications/unsubscribe-auth/AXROLOCJ7KFM3Q3JCODASDLYWZX3NAVCNFSM6AAAAABCRDLEGSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSNZZHEZDKNZYGE . You are receiving this because you were mentioned.Message ID: @.***>

-- Bill McSpadden Formal Verification Engineer RISC-V International mobile: 503-807-9309

Incarnation-p-lee commented 4 months ago

Hi Bill,

Hope you get better and recover soon. To port the TestFloat to the repo sail-riscv, Tim has a proposal requires some update in sail compiler if my understanding is correct.

The idea is that we can port these test cases to sail similar as SoftFloat and find a place to run/execute them(as one of the target of makefile).

ptomsich commented 4 months ago

The compiler changes would be required to automatically run both implementations (i.e., in lockstep) and compare the results.

The referenced [http://www.jhauser.us/arithmetic/TestFloat.html](Berkeley TestFloat) is a black-box FP test-suite. Having a test-suite for the IEEE-FP compliance in the repository (and running it as part of the CI/CD against the generated c_simulator) would be a great idea.

Incarnation-p-lee commented 4 months ago

Status Update Mar 18, 2024

jjscheel commented 4 months ago

@billmcspadden-riscv, please reach out to @Incarnation-p-lee and @haicheng-li about the Testing Process which has been proposed by the Golden Model SIG and how to proceed with this work. Thanks!

jjscheel commented 3 months ago

Note: We've extracted the verification work associated with the new Sail replacement for softfloat into issue #41. So, acceptance of this item will require successful passing of the verification work, but the actual work and discussion associated with building and performing the verification will be in the new issue.

Incarnation-p-lee commented 3 months ago

Table of contents

Floating Point API Design for Sail

[TOC]

Motivation

Currently the sail-riscv take the c-implemented softfloat to perform the floating-point related operations. However, it is not the sail code which can be transformed to any other modeling validation tools. Thus, we would like to replace the c-implemented softfloat into the sail native way.

Given that floating-point is one more general concept above the sail-riscv, it is even better to port the c-implemented softfloat as a standalone sail library and then integrated into the sail-riscv when fully verified.

Goal

Pull Request

API(s)

Exception and Rounding Modes

Floating-point Exception Flags

Flags NV DZ OF UF NX
Full-name invalid operation divide by zero overflow underflow inexact
Value 0b1 0b10 0b100 0b1000 0b10000

Floating-point Rounding Modes

Modes RNE RNA RDN RUP RTZ
Full-name round to nearest, ties to even round to nearest, ties to away round down round up round towards zero
Value 1 2 3 4 5

Mechanism

API Details

All API(s) support half, single and double precision floating-point, aka FP16, FP32 and FP64. Each API will leverage the existing rounding mode unless you explicit specific the rounding mode or by float_set_rounding before invoke the API. Meanwhile, the flags_mask allows you to mask some exception flags if you don't want it.

Type(s) Definition

Name Description
FP_N Floating-point with N bits, N can be 16, 32 or 64, aka half, single and double floating-point.
exception_flags Floating-point exception flags within 5 bits.
rounding_mode Floating-point rounding mode within 5 bits.
INT_N Signed Integer with N bits, N can be 16, 32 or 64.
UINT_N Unsigned Integer with N bits, N can be 16, 32 or 64.

float_is_nan

The floating-point is NAN or not, return true if NAN, or false.

bool float_is_nan (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_qnan

The floating-point is QNAN or not, return true if QNAN, or false.

bool float_is_qnan (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_snan

The floating-point is SNAN or not, return true if nan, or false.

bool float_is_snan (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_inf

The floating-point is infinite or not, return true if infinite, or false.

bool float_is_inf (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_positive

The floating-point is positive or not, return true if positive, or false.

bool float_is_positive (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_negative

The floating-point is negative or not, return true if negative, or false.

bool float_is_negative (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_zero

The floating-point is zero or not, return true if z,ero or false.

bool float_is_zero (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_normal

The floating-point is normal or not, return true if normal, or false.

bool float_is_normal (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_is_denormal

The floating-point is denormal or not, return true if denormal, or false.

bool float_is_denormal (FP_N);
Flags NV DZ OF UF NX
Raise N N N N N

float_eq

The floating-point equals, return true if op_1 is equal to op_2, or false.

(bool, exception_flags) float_eq ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_ne

The floating-point not equals, return true if op_1 is equal to op_2, or false. $$ (bool, flags) = op_1 \ne op_2 $$

(bool, exception_flags) float_ne ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_lt

The floating-point less than, return true if op_1 is less than op_2, or false.

(bool, exception_flags) float_lt ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_lt_quiet

Similar to float_lt but only raise NV when op_1 and/or op_2 is SNAN.

(bool, exception_flags) float_lt_quiet ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_le

The floating-point less than or equal, return true if op_1 is less than or equal to op_2, or false.

(bool, exception_flags) float_le ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_le_quiet

Similar to float_le but only raise NV when op_1 and/or op_2 is SNAN.

(bool, exception_flags) float_le_quiet ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_gt

The floating-point greater than, return true if op_1 is greater than op_2, or false.

(bool, exception_flags) float_gt ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_gt_quiet

Similar to float_gt but only raise NV when op_1 and/or op_2 is SNAN.

(bool, exception_flags) float_gt_quiet ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_ge

The floating-point greater than or equal, return true if op_1 is greater than or equal to op_2, or false.

(bool, exception_flags) float_ge ((FP_N, FP_N));
Flags NV DZ OF UF NX
Raise Y N N N N

float_ge_quiet

Similar to float_ge but only raise NV when op_1 and/or op_2 is SNAN.

(bool, exception_flags) float_ge_quiet ((FP_N, FP_N op_2));
Flags NV DZ OF UF NX
Raise Y N N N N

float_add

The floating-point add, aka:

(FP_N, exception_flags) float_add ((FP_N, FP_N));
(FP_N, exception_flags) float_add_by_config ((FP_N, FP_N), rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_sub

The floating-point sub, aka:

(FP_N, exception_flags) float_sub ((FP_N op_1, FP_N op_2));
(FP_N, exception_flags) float_sub_by_config ((FP_N, FP_N), rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_mul

The floating-point mul, aka:

(FP_N, exception_flags) float_mul ((FP_N, FP_N));
(FP_N, exception_flags) float_mul_by_config ((FP_N, FP_N), rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_div

The floating-point div, aka:

(FP_N, exception_flags) float_div ((FP_N, FP_N));
(FP_N, exception_flags) float_div_by_config ((FP_N, FP_N), rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y Y Y Y Y

float_mul_add

The floating-point mul_add, aka:

(FP_N, exception_flags) float_mul_add ((FP_N, FP_N, FP_N));
(FP_N, exception_flags) float_mul_add_by_config ((FP_N, FP_N, FP_N), rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_sqrt

The floating-point sqrt, aka:

(FP_N, exception_flags) float_sqrt (FP_N);
(FP_N, exception_flags) float_sqrt_by_config (FP_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_to_i32

The floating-point converting to signed INT_N, N = 32 aka:

(INT_N, exception_flags) float_to_i32 (FP_N);
(INT_N, exception_flags) float_to_i32_by_config (FP_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_to_i16

Almost the same as float_to_i32 except the INT_N bit size.

float_to_i64

Almost the same as float_to_i32 except the INT_N bit size.

float_to_u32

The floating-point converting to unsigned UINT_N, N = 32 aka:

(UINT_N, exception_flags) float_to_u32 (FP_N);
(UINT_N, exception_flags) float_to_u32_by_config (FP_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_to_u16

Almost the same as float_to_u32 except the UINT_N bit size.

float_to_u64

Almost the same as float_to_u32 except the UINT_N bit size.

float_from_s32

The floating-point converting from signed INT_N, N = 32 aka:

(FP_N, exception_flags) float_from_s32 (INT_N);
(FP_N, exception_flags) float_from_s32_by_config (INT_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_from_i16

Almost the same as float_from_i32 except the INT_N bit size.

float_from_i64

Almost the same as float_from_i32 except the INT_N bit size.

float_from_u32

The floating-point converting from unsigned UINT_N, N = 32 aka:

(FP_N, exception_flags) float_from_u32 (UINT_N);
(FP_N, exception_flags) float_from_u32_by_config (UINT_N, rounding_mode mode, exception_flags flags mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_from_u16

Almost the same as float_from_u32 except the UINT_N bit size.

float_from_u64

Almost the same as float_from_u32 except the UINT_N bit size.

float_to_f32

The floating-point converting to FP_N, N = 32 aka:

(FP_N, exception_flags) float_to_f32 (FP_N);
(FP_N, exception_flags) float_to_f32_by_config (FP_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_to_f16

Almost the same as float_to_f16 except the FP_N bit size.

float_to_f64

Almost the same as float_to_f16 except the FP_N bit size.

float_round_to_int

The floating-point round to nearest integer in FP_N, aka:

(FP_N, exception_flags) float_round_to_int (FP_N);
(FP_N, exception_flags) float_round_to_int_by_config (FP_N, rounding_mode mode, exception_flags flags_mask);
Flags NV DZ OF UF NX
Raise Y N Y Y Y

float_set_rounding

The floating-point set rounding modes.

(rounding_mode) float_set_rounding (rounding_mode mode);
Flags NV DZ OF UF NX
Raise N N N N N

Reference Link

Incarnation-p-lee commented 3 months ago

Hi @jjscheel and @billmcspadden-riscv

Just draft the API(s) of sail float, please feel free to comment if any questions or concerns.

CC @haicheng-li for awarness.

jjscheel commented 3 months ago

Nice, @Incarnation-p-lee. THANKS!

Incarnation-p-lee commented 3 months ago

Status Update Apr 16, 2024

jjscheel commented 2 months ago

@Incarnation-p-lee, how is the POC going?

Incarnation-p-lee commented 2 months ago

Status Update Apr 30, 2024

Incarnation-p-lee commented 2 months ago

@Incarnation-p-lee, how is the POC going?

Sorry for missing the status update, happy holiday, ;)!

jjscheel commented 2 months ago

No worries. Happy holiday to you!

Incarnation-p-lee commented 2 months ago

Hi @jjscheel Just FYI that all PR can be found around the end of the API design doc. For example:

image

Incarnation-p-lee commented 2 months ago

Status Update Mar 14, 2024

jjscheel commented 2 months ago

Thanks, @Incarnation-p-lee. Can you explain why your SAIL work is in the rems-project and not sail-riscv?

Incarnation-p-lee commented 2 months ago

Thanks, @Incarnation-p-lee. Can you explain why your SAIL work is in the rems-project and not sail-riscv?

We promote the float to a standalone lib, thus SAIL will be a better place here. Because not only sail-riscv can leverage this library.

jjscheel commented 2 months ago

Ah, yes! I now understand. Thanks, @Incarnation-p-lee!!!

Incarnation-p-lee commented 1 month ago

Status Update Mar 28, 2024

jjscheel commented 1 month ago

@Incarnation-p-lee, it appears ALL your PRs have now merged. Congrats. Does this mean your library is fully implemented?

jrtc27 commented 1 month ago

Compare the list of APIs to the much smaller list of things covered by the PRs that exist to date. It's a big chunk of work to get through.

Incarnation-p-lee commented 1 month ago

Thanks @jrtc27 for the explanation. That is correct, there are lots of API that need to be covered, I think the overall progress is about 10%, give or take.

Incarnation-p-lee commented 1 month ago

Status Update Jun 11, 2024

Incarnation-p-lee commented 1 month ago

Status Update Jun 25, 2024

Incarnation-p-lee commented 2 weeks ago

Status Update Jul 9, 2024