search

riscv-admin / dev-partners

This repo is for tracking of RISC-V Development Partners Activities
3 stars 0 forks source link

Zce architecture tests #6

Open jjscheel opened 1 year ago

jjscheel commented 1 year ago

Technical Group

Code Size Reduction TG

ratification-pkg

Code Size

Technical Liaison

Tariq Kurd

Task Category

Arch Tests

Task Sub Category

Ratification Target

1Q2023

Statement of Work (SOW)

SOW link

SOW Signoffs: (delete those not needed)

Waiver

Pull Request Details

No response

jjscheel commented 1 year ago

Per 4/11 email from Prasanna:

Code size reduction: First set of test cases are written, they are being tested against Spike, dei run is in progress until the tests are pass - in progress

ptprasanna commented 1 year ago

No progress made since last Call. Was busy on Zfinx.

jjscheel commented 1 year ago

Ok. Please keep this as a focus item. We need to start showing progress here.

ptprasanna commented 1 year ago

The dry of the tests designed was resumed against SPIKE, still seeing few failures. Fixing/Modifying the tests/frameworks is underway.

jjscheel commented 1 year ago

Glad we are once again making progress!

jjscheel commented 1 year ago

@ptprasanna, any update?

jjscheel commented 1 year ago

@pz9115, raising this to your attention as @ptprasanna is working a possible toolchain issue.

ptprasanna commented 1 year ago

Possibly an issue, but discussing with @Abdulwadoodd to get different point of view, before we conclude the issue with the tool chain. Also discussing with @pz9115 as well.

jjscheel commented 1 year ago

Feed back from @Abdulwadoodd:

Toolchain works fine for Zce. The error you are getting is because of illegal operands of instructions: The immediate offset of the instructions in the generated tests are incorrect. If you look at the spec, c.lb , c.lh instructions only allowed to have 2-bit unsigned immediate offset (at max) which is not the case for your tests and hence the compilation error. Do look the reserved lsb of unimm as well

You can try compiling the instruction like: c.lh x10, 0(x12) c.lh x8, 2(x13)

And it would work with the toolchain.

I hope this resolves your issue.

ptprasanna commented 1 year ago

Zcf - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating. Zcd - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating. Zcb - Tests are generated, but few cover-points are not meeting up, we are getting them sorted Zcmp - Yet to start the tests Zcmt - Yet to start the tests

jjscheel commented 1 year ago

Thanks, @ptprasanna! Will remove from Agenda for this week. Please feel free to reach out if you need technical assistance debugging.

jjscheel commented 1 year ago

@ptprasanna, please update status here.

anuani21 commented 1 year ago

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06 Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

  1. Use compile args -march= rv32imaf_zcf -mabi=ilp32f.
  2. As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

pz9115 commented 1 year ago

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06 Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

  1. Use compile args -march= rv32imaf_zcf -mabi=ilp32f.
  2. As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

Hi @anuani21, Can you provide the error log for me to learn more about the cause of the error, thanks.

anuani21 commented 1 year ago

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

pz9115 commented 1 year ago

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

Hi @anuani21, I found some compressed instructions that used in the log file, such as:

c.flw f15,-0x4(f15)
c.flw f14,0x0(f13)
c.flw f12,0x28(f11)

Where you use fpr as the second operand. As the instruction defination, it load from memory, computes an effective address by adding the zero-extended as offset scaled by 4.

So you should use gpr instead fpr as the second operand and set the offset positive and multiple it 4, such as:

c.flw f15,0x4(x15)
c.flw f14,0x0(x13)
c.flw f12,0x28(x11)
Abdulwadoodd commented 1 year ago

Hi @ptprasanna, @jjscheel

RISC-V Config PR is merged which adds support of Code size reduction extension to riscv-config tool PR link: https://github.com/riscv-software-src/riscv-config/pull/129

This was critical because RISCOF and ISAC use riscv config to run tests and generate coverage reports respectively. One can run Zce ACTs using RISCOF by updating the riscv-config version.

anuani21 commented 1 year ago

Hi @pz9115,

As per your suggestions,I have done all the changes.Tests are run successfully and got 100% coverage for all instructions in Zcf and Zcd extensions.

jjscheel commented 1 year ago

Great news. How is the coverage coming for other extensions?

ptprasanna commented 1 year ago

Zcb - Completed 100% Coverage Zcf - Completed 100% Coverage Zcd - Completed 100% Coverage Zcmp - @anuani21 is looking for some guidance or help from the community Zcmt - @anuani21 is looking for some guidance or help from the community

jjscheel commented 1 year ago

@tariqkurd-repo, can you help @anuani21 with their questions on Zcmp and Zcmt?

tariqkurd-repo commented 1 year ago

What are the questions?

anuani21 commented 1 year ago

Hi Tariqkurd,

I am working on zcmp and zcmt extensions in code size reduction. I have a few queries regarding the implementation of Zcmp and zcmt instructions.In other extensions Zcf and zcd,the val combinations using gen_sign_dataset , gen_unsign_dataset and abstract comb in cgf. But in Zcmp and zcmt instructions,how do we need to write the val combinations for those instructions in riscv-ctg.Can you please guide me and also send any reference cgf for those instructions?

tariqkurd-repo commented 1 year ago

Hi,

First, what is the status of Zcb, Zcd, Zcf? It's a trivial extension so can we push the SAIL and tests now?

In other extensions Zcf and zcd,the val combinations using gen_sign_dataset , gen_unsign_dataset and abstract comb in cgf.

What is cgf? I'll need some context, but note that I can only explain the spec not details of your specific implementation.

Tariq

On Tue, Oct 10, 2023 at 8:41 AM anuani21 @.***> wrote:

Hi Tariqkurd,

I am working on zcmp and zcmt extensions in code size reduction. I have a few queries regarding the implementation of Zcmp and zcmt instructions.In other extensions Zcf and zcd,the val combinations using gen_sign_dataset , gen_unsign_dataset and abstract comb in cgf. But in Zcmp and zcmt instructions,how do we need to write the val combinations for those instructions in riscv-ctg.Can you please guide me and also send any reference cgf for those instructions?

— Reply to this email directly, view it on GitHub https://github.com/riscv-admin/dev-partners/issues/6#issuecomment-1754596007, or unsubscribe https://github.com/notifications/unsubscribe-auth/AOCTJAA6CEES66N5NYL3KRDX6T3Z7AVCNFSM6AAAAAAV5WEWZ6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTONJUGU4TMMBQG4 . You are receiving this because you were mentioned.Message ID: @.***>

jjscheel commented 11 months ago

@ptprasanna, @anuani21, may I please have an update on the status?

jjscheel commented 11 months ago

@ptprasanna, I would like an update in the issue, by the next meeting on December 12, 2023, please.

anuani21 commented 11 months ago

Zcb - Completed 100% Coverage Zcf - Completed 100% Coverage Zcd - Completed 100% Coverage Zcmt - Generating the test case. Zcmp - Yet to start the test.

anuani21 commented 9 months ago

@jjscheel, Generating a test case for few instructions in Zcmp(cm.push,cm.pop,cm.popret and cm.popretz) and Zcmt (c.jalt).

The instructions(cm.mvsa01 and cm.mva01s) in Zcmp and Zcmt (c.jt).Tests generated and few coverpoints are not hiting so I am debugging to fix it up.

anuani21 commented 9 months ago

@jjscheel, Generating a test case for few instructions in Zcmp(cm.push,cm.pop,cm.popret and cm.popretz) and Zcmt (c.jalt).

Zcmp - (cm.mvsa01 and cm.mva01s instructions) Tests generated and got 100% coverage. Zcmt - Tests generated and got 100% coverage.

jjscheel commented 9 months ago

@anuani21, what work remains? Are we down to simply review of the tests and coverage reports?

anuani21 commented 8 months ago

@jjscheel , Here are the updates from IITM,

Zcmp extension: cm.mvsa01 - Completed with 100% coverage. cm.mva01s- Completed with 100% coverage. cm.push- Test generated and few coverpoints are not hitting. cm.pop - Test generated and few coverpoints are not hitting. cm.popret - yet to start the test. cm.popretz- yet to start the test.

Zcmt extension: c.jt- completed with 100% coverage. c.jalt- yet to start the test.

anuani21 commented 7 months ago

No progress made since last Call. Was busy on Debug Act for Native Triggers.

jjscheel commented 7 months ago

Will this be true until you complete the Debug work in April?

anuani21 commented 6 months ago

No progress.

jjscheel commented 6 months ago

@anuani21, thanks. When do you anticipate starting work here again?

anuani21 commented 6 months ago

I will start the work again by last week of April

On Tue, 16 Apr, 2024, 5:37 pm Jeff Scheel, @.***> wrote:

@anuani21 https://github.com/anuani21, thanks. When do you anticipate starting work here again?

— Reply to this email directly, view it on GitHub https://github.com/riscv-admin/dev-partners/issues/6#issuecomment-2058933621, or unsubscribe https://github.com/notifications/unsubscribe-auth/A3G6FF2FUCXC2ZKSCY5CZGDY5UIALAVCNFSM6AAAAAAV5WEWZ6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDANJYHEZTGNRSGE . You are receiving this because you were mentioned.Message ID: @.***>

jjscheel commented 6 months ago

Ok, thank you!

anuani21 commented 6 months ago

@jjscheel,

Restart the work of Zcmp and Zcmt extension by tomorrow.I will make progress on the task before the next meeting.

anuani21 commented 5 months ago

@jjscheel,

Updates from IITM, Zcmp extension:

cm.pop - Test generated and some coverpoints are not hitting. cm.popret - Generating the test. cm.popretz- Generating the test.

Zcmt extension:

c.jalt- Generating the test.

jjscheel commented 5 months ago

Thanks, Anusha. Please let me know if you need any assistance locating the gaps.

anuani21 commented 5 months ago

@jjscheel,

Updates from IITM,

Zcmp extension:

cm.mvsa01- Completed with 100% coverage(For RV32 and RV64). cm.mva01s -Completed with 100% coverage(For RV32 and RV64). cm.push - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32. cm.pop - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32. cm.popret -Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32. cm.popretz - Test generated for RV32 and RV64. In coverage, some register coverpoints are not met up in RV64 and RV32.

Zcmt extension: cm.jt -Completed and 100% coverage for RV32.

Pending work in Zcmp - I have to fix the register coverpoint issue.(I will fix the issue before next meeting). Pending work in Zcmt -  Cm.jalt instruction  for RV32 and RV64,cm.jt instruction for RV64.

anuani21 commented 4 months ago

@jjscheel,

Zcmt extension- Generating test cases for cm.jalt instruction in RV32 and RV64.

Pending work in Zcmp - I have to fix the register coverpoint issue.

anuani21 commented 3 months ago

@jjscheel,

No progress made since last call.

anuani21 commented 2 months ago

@jjscheel,

Updates from IITM,

Zcmt extension: cm.jt -Completed with 100%coverage for RV32 and RV64. cm.jalt - Completed with 100%coverage for RV32 and RV64

Pending work in Zcmp - I have to fix the register coverpoint issue.I will fix this issue before next meeting.

anuani21 commented 2 months ago

@jjscheel,

Updates from IITM, In Zcmp extension: cm.push- Completed with 100%coverage for RV32. cm.pop - Completed with 100%coverage for RV32. cm.popret -Need to fix the register coverpoints. cmpopretz- Need to fix the register coverpoints.

anuani21 commented 1 month ago

@jjscheel,

No progress made since last Call. Was busy on Debug ACT for Native Triggers.

anuani21 commented 1 month ago

@jjscheel,

Updates from IITM,

  1. Zcb -it is already merged.

  2. Zcf -Raised a PR.

  3. Zcd - Raised a PR.

  4. Zcmp - popret and popretz instructions are pending. 5.. Zcmt- completed. Need to raise a Pr along with zcmp extension

jjscheel commented 1 month ago

Great. THANKS!!!

anuani21 commented 3 weeks ago

@jjscheel,

Updates from IITM,

  1. Zcf&Zcd extension: Re-submiited the PR in riscv-ctg and riscv-isac into riscv-arch-test https://github.com/riscv-non-isa/riscv-arch-test/pull/497

  2. Zcmp and Zcmt extension: We will raise a PR within this week.

JAYANTH-IITM commented 1 week ago

Update : I am currently working on ACT for Zcmp and Zcmt .

While running the test I am encounter this assembler error which is saying "Zcm* is not compatible with C extension" . I have raised the same issue in arch-test repo (https://github.com/riscv-non-isa/riscv-arch-test/issues/543) in which allen suggested to include c in ISA ( RV32ICZicsr_Zca_Zcmp ) , but even after that the error was not resolved .

I asked tariq sir also about this error , to which sir suggested it might be toolchain bug.

@pz9115 sir can you please help me here . I have attched ss of the error Image