Open jjscheel opened 1 year ago
Per 4/11 email from Prasanna:
Debug : sangee status at where we were last, nothing progressed from our last meeting
Was busy on other items, same status as previous.
Will keep this on the Agenda for discussion as we work to find a way to offload this effort based on Zfinx, Zfh running long and new work in Zdinx and Zhinx.
I've started a discussion with @timsifive and @pdonahue-ventana to explore contingencies.
Because this work has stalled, setting to "Blocked".
Have Dusted off the debug ACT Matrix to finish the work at some quantifiable milestone. Shall send it for Tim's review before next meeting. This to complete the tasks which was started earlier, rather leave it in the middle.
We discussed this today in the Debug TG call without any takers. So, we shall see. Tim and Paul understand that without a volunteer, this may take us some time to get to.
@timsifive, @pdonahue-ventana, any volunteers to help here yet?
I haven't heard from anyone.
Comment from most recent ARC minutes (July 10) - link
- Debug 1.0: Review has started of the latest submitted spec, but just review of all the changes since the last Debug 1.0 draft spec was submitted, reviewed, and approved. Review of this has started, with initial discussion of one of the more notable backward-incompatible changes (between v1.0 and the ratified v0.13). This relates with abstract commands and the data registers to support more efficient FPGA implementations. After further discussion in next week's ARC meeting, John will be providing ARC feedback and guidance to the Debug TG. Likely other items of feedback that arise will also be provided.
- Review of the latest Debug and Pointer Masking specs (along with the S*deleg extensions) are expected to continue next week.
Also note, this remains on the list of future DevPartners activities. It will be addressed AFTER Pointer Masking and the Floating Point gap work work (Zdinx, Zhinx).
Assigning back to IITM now that Zfinx/Zfh/Zdinx/Zhinx are wrapping up.
@ptprasanna, please dust off the coverage matrix and begin working on tests using Spike or QEMU. Technical questions can be directed to @timsifive.
@ptprasanna, this item is getting close to Freeze. As such, I'd like to understand the progress we've made in our next meeting. Please either attend or post status at your earliest convenience.
@jjscheel - Here are the updates from IITM
Debugger existing test logs are placed in the below links:
https://gitlab.com/ptprasanna/actreports/-/tree/main/debugger/spike%2032?ref_type=heads in spike32. https://gitlab.com/ptprasanna/actreports/-/tree/main/debugger/spike%2064?ref_type=heads in spike64.
This is good news, @ptprasanna and @anuani21!
@timsifive, note the progress.
Note that all tests in riscv-tests/debug test debugging through an external debugger. None of them test native trigger behavior, where a trigger is set and when it is hit the hart takes a debug exception.
@ptprasanna, I would like an update in the issue, by the next meeting on December 12, 2023, please.
@jjscheel, Based on the coverage matrix, I have started writing tests for native trigger behavior.I will able to share the draft by next meeting.
@anuani21, may I please get an update here?
@timsifive ,Can you please guide me, how to run the tests in native trigger behaviour?
@jjscheel ,I have generated the test for instruction count trigger(type 3) based on the coverage matrix.
@timsifive, Can you please guide me, how to run the tests in native trigger behaviour in spike?
timsifive is now @rtwfroody
@rtwfroody , Can you please guide me, how to run the tests in native trigger behaviour in spike?
@anuani21, I've sent an email to Tim and cc'd you.
There's a README that describes how to run the tests: https://github.com/riscv-software-src/riscv-tests/blob/master/debug/README.md
If that's not clear, let me know.
@anuani21, please provide a status update when we have a moment. As I mentioned in the meeting, this work will gate ratification of the specification if not complete in the next 2-3 months.
@jjscheel, I will complete the work within the end of April month.
Here are the updates from IITM,
Based on the coverage matrix I am generating the test cases for trigger type 2 (match control) and type 3(instruction count) with different set of arguments.
I will share the draft to @rtwfroody for review shortly.
Based on the coverage matrix I am generating the test cases for trigger type 2 (match control) and type 3(instruction count) with different set of arguments.
We should focus on type 6 rather than type 2. Type 2 says: "This trigger type is deprecated. It is included for backward compatibility with version 0.13." Type 6 says: "This replaces mcontrol in newer implementations and serves to provide additional functionality."
Thanks, @anuani21 and @pdonahue-ventana!
@paul, we need to write the test cases for trigger type 6 and trigger type 3 alone.
On Mon, 18 Mar, 2024, 9:00 pm Paul Donahue, @.***> wrote:
Based on the coverage matrix I am generating the test cases for trigger type 2 (match control) and type 3(instruction count) with different set of arguments.
We should focus on type 6 rather than type 2. Type 2 says: "This trigger type is deprecated. It is included for backward compatibility with version 0.13." Type 6 says: "This replaces mcontrol in newer implementations and serves to provide additional functionality."
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@jjscheel, Based on the coverage matrix I am generating the test cases for trigger type 6 (match control6) and type 3(instruction count) with different set of arguments.
@jjscheel,
Updates from IITM,
I will share the above tests and logs to @rtwfroody for review shortly.
In trigger type 6, the following tests are pending
I will complete the pending tests before the next meeting.
@anuani21, this is great progress. Am I correct in understanding that work remains on trigger type = 3?
Yes, that is correct. Type 3 test is pending.
On Tue, 2 Apr, 2024, 6:11 pm Jeff Scheel, @.***> wrote:
@anuani21 https://github.com/anuani21, this is great progress. Am I correct in understanding that work remains on trigger type = 3?
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I will share the above tests and logs to @rtwfroody for review shortly.
I never saw this. Did I miss an email somewhere?
Hi,
I had completed the test cases for store and execute with different match values ranges from 0 to 5 in trigger type 6.
In load operation, I am facing some issues, once it complete I will share the entire trigger type 6 test cases for review.
On Mon, 15 Apr, 2024, 10:47 pm Tim Newsome, @.***> wrote:
I will share the above tests and logs to @rtwfroody https://github.com/rtwfroody for review shortly.
I never saw this. Did I miss an email somewhere?
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@jjscheel,
Updates from IITM,
Based on the coverage matrix, I have generated test cases for match control( type 6) triggers, where the trigger is set with parameters (store=1 and load=1 and set of match values[0,1,2,3,4,5]) when the trigger is hit , then the hart takes a debug exception and it perform different action based on the match values.
The pending test cases are,
Type3 trigger test cases.
In Type6 trigger when load =1 and match=0 facing some issue in this test cases, I will fix this issue.
when the above issue fixed in type 6 trigger, i will share the entire trigger 6 test cases and logs for review to @rtwfroody.
@jjscheel, Updates from IITM ,
-Paul suggested checking tinfo.version bit upon checking tinfo.version == 0 which means it is running in older version ( 0.13 ) , but the debug spec says to run in newer version ( 1.0 ) in which tinfo.version = 1 .
-After updating both spike and openocd to the latest commit , raised the same issue in openocd (https://github.com/riscv-collab/riscv-openocd/issues/1053) to which got the response stating this could be a spike issue.
-Raised the same issue in spike ( https://github.com/riscv-software-src/riscv-isa-sim/issues/1651#issuecomment-2084430295) . This issue seems not yet to be addressed in the spike development forum .
Can we get additional help regarding this issue ?
@pdonahue-ventana, @rtwfroody, please see the past post and advice @anuani21 on how to work past the issue.
I'll update the spike trigger implementation to implement hit0/hit1 instead of the timing bit for mcontrol6. Should be done by May 15.
Have sent the test case and logs for trigger 6 (with load store and execute operations ) in older version for review to @rtwfroody.
How did you send these? I haven't seen them.
Tims, can you please send your mail address so that i can send it once again.
On Wed, 1 May, 2024, 9:45 pm Tim Newsome, @.***> wrote:
I'll update the spike trigger implementation to implement hit0/hit1 instead of the timing bit for mcontrol6. Should be done by May 15.
Have sent the test case and logs for trigger 6 (with load store and execute operations ) in older version for review to @rtwfroody https://github.com/rtwfroody.
How did you send these? I haven't seen them.
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My email address is tim@casualhacker.net.
@jjscheel,
Updates from IITM ,
Following the review done by @rtwfroody ,by ongoing work in debug task
1) We are waiting for the fix in spike for mcontrol6. Tims informed me this fix will be done by this week. 2) Parallelly we are going to revisit the written tests and follow a new flow. 3) I am writing the test cases for type 3 trigger. Once the fix is in place we will resume to run the tests
I have a spike branch that updates the mcontrol6 to version 1.0. @anuani21, can you use this branch for your mcontrol6 tests? It should be correct, but since there are no tests there may be bugs. If it's behaving strangely, please send me the test you're working on and I'll look into it.
The pull request (which I won't pursue further until I get confirmation that this code passes the new tests) is at https://github.com/riscv-software-src/riscv-isa-sim/pull/1667.
@rtwfroody, Fix for mcontrol6 in spike which updatesthe version to 1.0 is working fine. @rtwfroody and @jjscheel, I have started revisit the written test for mconrol6 type trigger and other trigger types.
Hello there,
I provided the source code of trigger type 3~6 to Spike last year (based on type 2 originally provided by @rtwfroody).
Sorry that I overlooked the tinfo.version. Since you are using the trigger module in Spike. I want to say hi to you, and let you know that I am willing to provide additional commits for bugs in my code.
@YenHaoChen's mcontrol6.hit{0,1} changes merged into spike mainline through https://github.com/riscv-software-src/riscv-isa-sim/pull/1257.
@anuani21, please use the latest version of spike for your testing. Since his implementation is different from mine, it might not act the same.
@anuani21, what is the latest status here? When do you project having PRs to submit?
Hi Jeff,
Due to some emergency situation, I am not available last week. From yesterday I am started the work again.
I will make progress on this issue and update you.
On Tue, 28 May, 2024, 11:28 pm Jeff Scheel, @.***> wrote:
@anuani21 https://github.com/anuani21, what is the latest status here? When do you project having PRs to submit?
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No worries, @anuani21. Hope all is well. Thanks for the update.
@jjscheel,
Updates from IITM ,
1)Implemented mcontrol6 trigger with the latest spike version , raised a few issues with Tim . Tim has informed that the issues will be fixed by june 24th . We can move forward only after the fix.
Noted few more issue , hoping to receive some fix / clarification
a) In the log generated , it is showing tcontrol could fetch register 'tcontrol' . While implementing trigger passing ebreak statement manually , mcause value 2 which is mapped to illegal instruction operation .
b) In the log dcsr value is 0x4000b083 this results in the dcsr.ebreakm bit set to 1 , which is mapped to debug mode . dcsr.ebreakm bit should be 0 , only then it will raised breakpoint exception
2)Parallel till then will work on Code Size Reduction , will pick up from the last update.
Technical Group
Debug TG
ratification-pkg
Debug
Technical Liaison
Tim Newsome
Task Category
Arch Tests
Task Sub Category
Ratification Target
3Q2023
Statement of Work (SOW)
SOW link
SOW Signoffs: (delete those not needed)
Waiver
Pull Request Details