Debug SAIL for Native Triggers

[jjscheel]

Technical Group

Debug TG

ratification-pkg

Debug

Technical Liaison

Tim Newsome

Task Category

SAIL model

Task Sub Category

• [ ] gcc
• [ ] binutils
• [ ] gdb
• [ ] intrinsics
• [ ] Java
• [ ] KVM
• [ ] ld
• [ ] llvm
• [ ] Linux kernel
• [ ] QEMU
• [ ] Spike

Ratification Target

3Q2023

Statement of Work (SOW)

SOW link

SOW Signoffs: (delete those not needed)

• Task group liaison sign-off date:
• Development partner sign-off date:

Waiver

• [ ] Freeze
• [ ] Ratification

Pull Request Details

• Sail PR

[jjscheel]

@junambi, as you begin to start this work, I'd appreciate an outlook for when you think this work might be completed. I suggest we think about it in terms of steps and put dates for each:

• [ ] Planning complete
• [ ] Development completed (ready to submit first PR)
• [ ] All PRs accepted (done)

[junambi]

Working on a flow for the implementation.

[jjscheel]

@timsifive, @pdonahue-ventana, any volunteers to help here yet?

[timsifive]

I haven't heard from anyone.

[jjscheel]

Comment from most recent ARC minutes (July 10) - link

• Debug 1.0: Review has started of the latest submitted spec, but just review of all the changes since the last Debug 1.0 draft spec was submitted, reviewed, and approved. Review of this has started, with initial discussion of one of the more notable backward-incompatible changes (between v1.0 and the ratified v0.13). This relates with abstract commands and the data registers to support more efficient FPGA implementations. After further discussion in next week's ARC meeting, John will be providing ARC feedback and guidance to the Debug TG. Likely other items of feedback that arise will also be provided.
• Review of the latest Debug and Pointer Masking specs (along with the S*deleg extensions) are expected to continue next week.

Also note, this remains on the list of future DevPartners activities. It will be addressed AFTER Pointer Masking and the Floating Point gap work work (Zdinx, Zhinx).

[jjscheel]

@UmerShahidengr, any chance that 10xEngineers has someone to pick this up and drive to conclusion?

[jjscheel]

@UmerShahidengr, any feedback on your ability to start work here?

[UmerShahidengr]

@muhammad-maarij-zeeshan can you please look at it? @jjscheel we will do it, you can change its status and set up its end date to be end of 2Q2024 (i.e, June 2024)

[jjscheel]

Thanks, @UmerShahidengr. Can you please make sure that @muhammad-maarij-zeeshan sends an email to info@riscv.org to request his account? Then, I'll take care of the other DevPartner enablement.

[jjscheel]

@UmerShahidengr, has work started here?

[UmerShahidengr]

@jjscheel it has not been started yet because of resource limitation, but it is in my priority list. Keep it assigned to me, I will look into it soon.

[jjscheel]

Thanks, @UmerShahidengr. As we discussed, we will need to complete the code to the point of submitting a PR in order to be able to ratify the spec without a waiver from the TSC. Given that the spec has completed Public Review and is being updated, it could be ready for ratification within the next 1-2 months.

[jjscheel]

@UmerShahidengr, any progress here?

[UmerShahidengr]

@jjscheel we will add the 1st PR within next 2 weeks.

[UmerShahidengr]

Update April 30th, 2024: @HAMZA-AFZAL404 has been working on this SoW. We are still in developing phase.

[UmerShahidengr]

@jjscheel, I have a query for this issue, We have been adding the functionality of every trigger register (Registers have been implemented) but, every trigger register is accessed by Debug Mode and Debug Mode is not implemented at all in Sail. Implementing full Debug Mode in Sail is a big problem as it has a huge spec and a huge stuff is to be implemented. My question is what is the scope of this SoW? Is it just to add the functionality of the trigger registers and making them writable in M mode? Or to implement full Debug Mode and then extend it for trigger? According to SoW, the requirement is to extend the SAIL model to implement the Trigger Module in Debug spec 1.0, but there is a confusion around the implementation of Debug Mode. CC: @HAMZA-AFZAL404

[jjscheel]

@UmerShahidengr, my understanding of the intent of this SOW is only to implement the Trigger Module to best of the support of EVERY register possible. While we are here, if we can extend the base register support with reasonable work, please do so as a separate PR, but you need not feel like you have to cover unimplemented registers. Those can come in when ready.

@billmcspadden-riscv, do you agree?

@timsifive and @pdonahue-ventana , does this meet your expectations?

[pdonahue-ventana]

I think that there's no need to implement trace-related actions and there's no need to implement Debug Mode which is not directly related to the Trigger Module. You can't get into Debug Mode without implementing non-ISA features like the Debug Module which are beyond the scope of SAIL. Therefore, the goal would be to implement triggers with action=0 and dmode=0. Just native (self-hosted) debug.

[jjscheel]

@HAMZA-AFZAL404, any updates on your progress?

[martinberger]

@pdonahue-ventana It's perfectly possible to implement the ISA part of most of the debug specs in Sail, so that you can run an RTL implementation of the debug module against it. Sail is a really good language for doing this, because of its excellent support for bit manipulation.

Due to the complex legalisation of Sdtrig CSRs, I think the YAML-based approach to model configuration will not scale to Sdtrig.

[pdonahue-ventana]

Due to the complex legalisation of Sdtrig CSRs, I think the YAML-based approach to model configuration will not scale to Sdtrig.

You're probably right.

[UmerShahidengr]

Update June 11th, 2024: The Native Trigger PR is available here, since Debug mode is not available in Sail so only register definitions (tdata1, tdata2 etc.) could have been added as part of Sdtrig extension. @Mudassir10X has worked on this, and he has been in contact with @billmcspadden-riscv on this implementation.

[jjscheel]

Thanks for update, @UmerShahidengr!

@billmcspadden-riscv, how difficult is it going to be implement basic debug mode?

[UmerShahidengr]

Update June 25th,2024: We had a meeting with Tim Newsome and @billmcspadden-riscv almost 10 days ago, and we discussed the logistics of Sdtrig implementation, we have concluded that basic native trigger support can be added in Sail without adding Debug mode support, @Mudassir10X has been working on this one, and we will be having meetings with Tim Newsome and Bill every 15 days to discuss the progress. So far, the basic task list has already been defined, we will keep you updated with the progress.

[UmerShahidengr]

Update July 23rd, 2024: Unfortunately @Mudassir10X is no longer working with 10xEngineers, there has been no update on this SoW. New team member will be assigned to this project and that new person will complete it.

[jjscheel]

Thanks for the update, @UmerShahidengr. I know this is unplanned, but please make this your (near) top priority to find a replacement. The waiver work has become the critical path to ratification for the Debug specification and this is one piece of it.

[UmerShahidengr]

Update August 6th, 2024 No major update on it. One trainee has been assigned as replacement of Mudassir, but it will take some time to ramp him up for this task.

[jjscheel]

@UmerShahidengr, per my email, we need to understand who the trainee is and how soon they will be able to work with @billmcspadden-riscv to complete this work.

[UmerShahidengr]

@jjscheel, after your email, we (Bilal and I) had conversation, one engineer will start working on this project full time from Sept 1st, we are estimating it to complete it till mid-October.

[UmerShahidengr]

@YazanHussnain-10x will be working on this SoW full time from Sept 1st.

CC: @jjscheel

[jjscheel]

Please ensure that Yazan applies for a RISC-V Portal id by sending an email to info@riscv.org with me on cc. I'll handle everything else after that. Welcome, YazanHussnain-10x!

[jjscheel]

Ping: Please ensure that Yazan applies for a RISC-V Portal id by sending an email to info@riscv.org with me on cc. I'll handle everything else after that. Welcome, YazanHussnain-10x!