New Landscape Entry - µRV32, MicroRV32

[saahm]

Project Name

µRV32 - MicroRV32

Description

µRV32 is a bundle of a SpinalHDL based RTL implementation of the RISC-V ISA and a SystemC TLM 2.0 based VP of the RTL model. The platform is built for the use on FPGAs and aims for research and educational use. The VP enables fast development and design exploration cycles for software development and hardware extensions of the ISA or the platform.

Homepage URL

https://agra.informatik.uni-bremen.de/projects/risc-v/

Crunchbase URL (https://www.crunchbase.com/)

No crunchbase URL available

Repository URL

https://github.com/agra-uni-bremen/microrv32

Organization hosting or owning the project

Group of Computer Architecture, University of Bremen

Evidence of RISC-V ecosystem support

On the homepage we host an updated list of our peer reviewed related publications, which were published in journals, conferences and workshops. Additionally, other research groups utilize our implementations in various degrees for education and lecturing, as well as research work on their own. We can provide more information if needed.

Logo

[No logo available at this time]()

Category

Implementations

[github-actions[bot]]

Thank you for requesting a new entry to be added, @saahm! Consider also adding this entry at RISC-V Exchange.

[github-actions[bot]]

Thank you for requesting a new entry to be added, @saahm! Consider also adding this entry at RISC-V Exchange.

[saahm]

Apparently the University of Bremen has a Crunchbase URL: https://www.crunchbase.com/organization/university-of-bremen-2

[andyjohnstonmoore]

+1 for IP implementation

[rpsene]

• 1 we are good to go @bprestonlf !