Not able to run RV32E Variant

[rahulraveendran15-coder]

Hi, I am not able to run RV32E variant of my sample test case with OVPSim simulator. I tried building the riscv elf tool chain with the following command:

./configure --prefix=$HOME/.local/opt/riscv32/riscv-gnu-toolchain/bin --with-arch=rv32emc --with-abi=ilp32e
make

Then creating the executable file with the command : riscv32-unknown-elf-gcc -o hello_world hello_world.c FInally when running the OVPsim with the sample script given as below:

#!/bin/bash

cd $(dirname $0)
bindir=$(dirname $(dirname $(pwd)))/bin/Linux64

${bindir}/riscvOVPsim.exe \
    --program hello_world \
    --variant RV32E \
    --override riscvOVPsim/cpu/add_Extensions=MACSU \
    "$@"

The error is as below:

Could anyone please help me on this

[jstraus59]

Could you please provide the elf file that is failing?

[rahulraveendran15-coder]

Hi @jstraus59 , Please find the attached elf file. I have gone through issue #20 but there it seems the tool chain was not of RV32E arch, in my case I built tool chain with RV32E. Still the issue is there.

hello.zip

[jstraus59]

By adding --trace to the riscvOVPsim command line I see the following:

...
Info 'riscvOVPsim/cpu', 0x000000000001baf2(_fstat): f6c10113 addi    sp,sp,-148
Info 'riscvOVPsim/cpu', 0x000000000001baf6(_fstat+4): c526     sw      s1,136(sp)
Info 'riscvOVPsim/cpu', 0x000000000001baf8(_fstat+6): 84ae     mv      s1,a1
Info 'riscvOVPsim/cpu', 0x000000000001bafa(_fstat+8): 00b10593 addi    a1,sp,11
Info 'riscvOVPsim/cpu', 0x000000000001bafe(_fstat+c): c906     sw      ra,144(sp)
Info 'riscvOVPsim/cpu', 0x000000000001bb00(_fstat+e): c722     sw      s0,140(sp)
Info 'riscvOVPsim/cpu', 0x000000000001bb02(_fstat+10): 99e1     andi    a1,a1,-8
Info 'riscvOVPsim/cpu', 0x000000000001bb04(_fstat+12): 4601     li      a2,0
Info 'riscvOVPsim/cpu', 0x000000000001bb06(_fstat+14): 4681     li      a3,0
Info 'riscvOVPsim/cpu', 0x000000000001bb08(_fstat+16): 4701     li      a4,0
Info 'riscvOVPsim/cpu', 0x000000000001bb0a(_fstat+18): 4781     li      a5,0
Info 'riscvOVPsim/cpu', 0x000000000001bb0c(_fstat+1a): 05000293 addi    t0,zero,80
Info 'riscvOVPsim/cpu', 0x000000000001bb10(_fstat+1e): 00000073 ecall
Internal Abort (VMIRTASRT) /home/build/DailyBuild/HEAD/Linux/Opt/Imperas/SimCommon/source/vmiStubs/vmiRt.c:2210:vmirtRegRead : NULL regDesc

The problem is that the toolchain is generating code using the ilp32e ABI, which is not supported by riscvOVPsim.

This ABI has not been standardized yet (The gcc RISC-V Oprions documentation states: There is also the ‘ilp32e’ ABI that can only be used with the ‘rv32e’ architecture. This ABI is not well specified at present, and is subject to change.)

I have confirmed it is possible to run this example using the full OVPsim simulator with the following command line:

iss.exe --program hello --variant RV32E --override iss/cpu0/add_Extensions=MACSU --processorname riscv --processorvendor riscv.ovpworld.org --semihostname riscv32Newlib

This works because the riscv32Newlib semihost selected here intercepts the _fstat function call, rather than supporting the Risc-V Proxy Kernel ecall convention.

Using OVPsim requires registering on the OVPsim website, obtaining a license for OVPsim (free for educational or evaluation purposes) and downloading and installing the OVPsim package.

[rahulraveendran15-coder]

Hi @jstraus59 , Thank you very much for the solution. We are using the ibex core for our thesis and in that the OVPsim simualtor is used which is pointing to this repository by the settings file. So if I am downloading the OVPsim from the website is it possible to link that full OVPsim simulator with with the ibex dv setup?

[jstraus59]

Does the Ibex dv setup use C programs or just assembly? If just assembly then the ABI is not an issue. If that is the case then you should be able to use riscvOVPsim.

[rahulraveendran15-coder]

ibex dv setup is using a dv instruction generator which generates assembly but in our thesis we are using c programs which will compile to assembly and then later the .bin is putting into ibex core and OVPsim.

Does the OVPsim simualtor you mentioned for the fix "iss.exe" is same as the one in the repository here, because I am not able to find iss.exe in the OVPsim slone here.

[jstraus59]

Not sure I understand your question.

riscvOVPsim is a free, unlicensed standalone RiscV-only ISS - but it does not include the iss.exe program I referenced.

iss.exe is part of the OVPsim product from Imperas, which requires registration and a license, and includes many capabilities and features not available in the free riscvOVPsim.

Imperas has a university program to make their full tools available at no charge for research purposes.

[rahulraveendran15-coder]

Thank you for the reply @jstraus59 I have registered in imperas site you mentioned, what should I need to use iss.exe or the full version of ovpsim which includes a license. can I use the same OVPsim from github or will it be in any other package?

Do you mean the iss.exe is a part of OVPsim or it it part of separate simulaotr of Imperas which is named as ISS(https://www.imperas.com/iss-imperas-instruction-set-simulator) or is it OVPsim plus?