How to get Each Risc-v instruction's machine cycle & respective size of Instruction's

[cghalibkhan]

Hi Every one,

• Actually, i want to know Risc-v Instructions machine cycle and their respective size.
• I have gone through many site's but still didn't get any info on it.

• Downloaded the datasheet from Riscv web site in that also there is nothing about instruction cycle & size.

  • can anyone Help to get machine cycles of Riscv architecture?
  • I compiled code using riscv64-unknown-linux-gnu-gcc
  • Run that executable on Hifive Unleashed Board U540, it's frequency if 1.5GHz

Thanks, Ghalib khan.

[jim-wilson]

Cycles per instruction depends on the target hardware. You would have to check the hardware documentation for the target.

It isn't clear what you mean by instruction size. Instructions are 32-bit in the base architecture, and some instructions have a 16-bit encoding in the C (compressed) extension. If you use objdump -dr to disassemble, it will show you whether instructions are two or 4 bytes. Instruction data can be 32-bit for the rv32i base architecture and 64-bit for the rv64i base architecture.

If you want machine cycles, you need to use a cycle accurate simulator. Or alternatively, you can try reading the cycle (and for rv32 cycleh) registers.

[cghalibkhan]

Hi good morning,

1> I check hardware Documents, in that there is no cycle info in it.

2> I checked cycle-accurate simulator, but it's showing a paid version of simulators, & am not sure that those simulators are for Risc-v arch compactable.

Help me to sort this issue.

Thanks, khan.

[jim-wilson]

Different implementations of the RISC-V architecture have different cycle timing. I can't help you with that. You must choose an implementation first, and then look for info on that implementation. You haven't clearly specified an implementation.

If you can get access to rtl or verilog, then you can do cycle accurate simulations. This type of simulation will be slow. You have to have detailed hardware info to get a cycle accurnate simulator, which means it has to be a hardware vendor simulator, or a rtl/verilog style simulator. Otherwise, you can't get cycle accurate simulation results.

As a compiler guy, I can only offer vague approximations, e.g. most alu instructions will be single cycle, multiply will be a few to several cycles, divide will be a few to several times slower than multiply, load/stores will be 2 cycles or slower, and FP instructions if present will probably be a few times slower than the corresponding integer instructions. But this stuff will all depend on the target, and can vary greatly from one target to the next.

You did mention the SiFive U540, and the SiFive u540 docs do have some hardware timing info in them. But this isn't a forum for SiFive u540 discussions.

I already pointed you at the cycle counter csr which is a way to get info from the hardware if you have hardware.

[lazyparser]

@cghalibkhan Hello, have you got the result you want?

[cghalibkhan]

No.

---

From: Wei Wu notifications@github.com Sent: 04 March 2021 4:02 PM To: riscv/riscv-gnu-toolchain riscv-gnu-toolchain@noreply.github.com Cc: Ghalib Khan ghalib.khan@exaleapsemi.com; Mention mention@noreply.github.com Subject: Re: [riscv/riscv-gnu-toolchain] How to get Each Risc-v instruction's machine cycle & respective size of Instruction's (#487)

@cghalibkhanhttps://github.com/cghalibkhan Hello, have you got the result you want?

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[TommyMurphyTM1234]

No update/activity in over a year and it seems that @jim-wilson already adequately addressed the issue. No RISC-V GCC toolchain issue identified.