Closed l1onog closed 6 months ago
TommyMurphyTM1234
commented
6 months ago Open On-Chip Debugger 0.10.0+dev-00830-ga88cc98a0-dirty (2024-04-09-21:46)
You're using a very out of date version of OpenOCD.
There have been a lot of changes/enhancements since that version that could impact behaviour in this context.
You should try again with a more up to date version - ideally a build of the latest 0.12.0+dev using the sources from this repository.
l1onog
commented
6 months ago When I use the latest version, I get the following results
Open On-Chip Debugger 0.12.0+dev-03744-g3991492cc (2024-04-15-21:35)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi channel' not 'ftdi_channel'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
riscv
riscv authdata_read [index]
riscv authdata_write [index] value
riscv dm_read reg_address
riscv dm_write reg_address value
riscv dmi_read address
riscv dmi_write address value
riscv dump_sample_buf [base64]
riscv etrigger set [vs] [vu] [m] [s] [u] <exception_codes>|clear
riscv exec_progbuf instr1 [instr2 [... instr16]]
riscv expose_csrs n0[-m0|=name0][,n1[-m1|=name1]]...
riscv expose_custom n0[-m0|=name0][,n1[-m1|=name1]]...
riscv hide_csrs {n0|n-m0}[,n1|n-m1]......
riscv icount set [vs] [vu] [m] [s] [u] [pending] <count>|clear
riscv info
riscv itrigger set [vs] [vu] [nmi] [m] [s] [u] <mie_bits>|clear
riscv memory_sample bucket address|clear [size=4]
riscv repeat_read count address [size=4]
riscv reset_delays [wait]
riscv resume_order normal|reversed
riscv set_bscan_tunnel_ir value
riscv set_command_timeout_sec [sec]
riscv set_ebreakm [on|off]
riscv set_ebreaks [on|off]
riscv set_ebreaku [on|off]
riscv set_enable_trigger_feature [('eq'|'napot'|'ge_lt'|'all')
('wp'|'none')]
riscv set_enable_virt2phys on|off
riscv set_enable_virtual on|off
riscv set_ir [idcode|dtmcs|dmi] value
riscv set_maskisr ['off'|'steponly']
riscv set_mem_access method1 [method2] [method3]
riscv set_reset_timeout_sec [sec]
riscv use_bscan_tunnel value [type]
riscv.cpu
riscv.cpu arm
riscv.cpu arm semihosting ['enable'|'disable']
riscv.cpu arm semihosting_basedir [dir]
riscv.cpu arm semihosting_cmdline arguments
riscv.cpu arm semihosting_fileio ['enable'|'disable']
riscv.cpu arm semihosting_read_user_param
riscv.cpu arm semihosting_redirect (disable | tcp <port>
['debug'|'stdio'|'all'])
riscv.cpu arm semihosting_resexit ['enable'|'disable']
riscv.cpu arp_examine ['allow-defer']
riscv.cpu arp_halt
riscv.cpu arp_halt_gdb
riscv.cpu arp_poll
riscv.cpu arp_reset 'assert'|'deassert' halt
riscv.cpu arp_waitstate statename timeoutmsecs
riscv.cpu cget target_attribute
riscv.cpu configure [target_attribute ...]
riscv.cpu curstate
riscv.cpu debug_reason
riscv.cpu eventlist
riscv.cpu examine_deferred
riscv.cpu get_reg list
riscv.cpu invoke-event event_name
riscv.cpu mdb address [count]
riscv.cpu mdd address [count]
riscv.cpu mdh address [count]
riscv.cpu mdw address [count]
riscv.cpu mwb address data [count]
riscv.cpu mwd address data [count]
riscv.cpu mwh address data [count]
riscv.cpu mww address data [count]
riscv.cpu read_memory address width count ['phys']
riscv.cpu riscv
riscv.cpu riscv authdata_read [index]
riscv.cpu riscv authdata_write [index] value
riscv.cpu riscv dm_read reg_address
riscv.cpu riscv dm_write reg_address value
riscv.cpu riscv dmi_read address
riscv.cpu riscv dmi_write address value
riscv.cpu riscv dump_sample_buf [base64]
riscv.cpu riscv etrigger set [vs] [vu] [m] [s] [u]
<exception_codes>|clear
riscv.cpu riscv exec_progbuf instr1 [instr2 [... instr16]]
riscv.cpu riscv expose_csrs n0[-m0|=name0][,n1[-m1|=name1]]...
riscv.cpu riscv expose_custom n0[-m0|=name0][,n1[-m1|=name1]]...
riscv.cpu riscv hide_csrs {n0|n-m0}[,n1|n-m1]......
riscv.cpu riscv icount set [vs] [vu] [m] [s] [u] [pending]
<count>|clear
riscv.cpu riscv info
riscv.cpu riscv itrigger set [vs] [vu] [nmi] [m] [s] [u]
<mie_bits>|clear
riscv.cpu riscv memory_sample bucket address|clear [size=4]
riscv.cpu riscv repeat_read count address [size=4]
riscv.cpu riscv reset_delays [wait]
riscv.cpu riscv resume_order normal|reversed
riscv.cpu riscv set_bscan_tunnel_ir value
riscv.cpu riscv set_command_timeout_sec [sec]
riscv.cpu riscv set_ebreakm [on|off]
riscv.cpu riscv set_ebreaks [on|off]
riscv.cpu riscv set_ebreaku [on|off]
riscv.cpu riscv set_enable_trigger_feature
[('eq'|'napot'|'ge_lt'|'all') ('wp'|'none')]
riscv.cpu riscv set_enable_virt2phys on|off
riscv.cpu riscv set_enable_virtual on|off
riscv.cpu riscv set_ir [idcode|dtmcs|dmi] value
riscv.cpu riscv set_maskisr ['off'|'steponly']
riscv.cpu riscv set_mem_access method1 [method2] [method3]
riscv.cpu riscv set_reset_timeout_sec [sec]
riscv.cpu riscv use_bscan_tunnel value [type]
riscv.cpu set_reg dict
riscv.cpu smp [on|off]
riscv.cpu smp_gdb
riscv.cpu was_examined
riscv.cpu write_memory address width data ['phys']
/opt/riscv/pulp/fpga/pulp-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg:24: Error:
in procedure 'script'
at file "embedded:startup.tcl", line 28
at file "/opt/riscv/pulp/fpga/pulp-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg", line 24
Error: [riscv.cpu] Unsupported DTM version: -1
Error: [riscv.cpu] Could not identify target type.Also, the contents of my cfg file
adapter_khz 1000
# Digilent JTAG-HS2
interface ftdi
ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
set _CHIPNAME riscv
jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511c3
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba on
# dump jtag chain
scan_chain
init
halt
echo "Ready for Remote Connections"So, it looks like my hardware connection is all good. Could the issue be with openocd or the cfg file? How should I tweak it? Thanks a ton for all your help!
TommyMurphyTM1234
commented
6 months ago You need to update/fix your OpenOCD debug script due to changes to some commands between 0.10.0 and 0.12.0. If you're not clear on what to do then refer to the latest OpenOCD documentation.
l1onog
commented
6 months ago If the version of opoencd corresponds to the version of the debug script, can we ignore the specific version issue, and how can we solve the 'examine(): Debug Module did not become active. dmcontrol=0x0' problem?
TommyMurphyTM1234
commented
6 months ago If the version of opoencd corresponds to the version of the debug script, can we ignore the specific version issue
No. Because, as I said, there have been many changes, enhancements and fixes between 0.10.0 and the latest 0.12.0 development version and these make it effectively pointless to report and analyse issues with the old version. You need to get things working with the latest 0.12.0 and see if the problem persists with that. It's not that difficult to update your script and I've given you the documentation link to assist with this.
l1onog
commented
6 months ago Thanks, I will try it as you pointed out.
TommyMurphyTM1234
commented
6 months ago @l1onog can you clarify what happened please? Did it work ok with a build of the latest OpenOCD once your OpenOCD script was updated to work with that?
I implemented RISCV SoC on a Zcu102 fpga. I am trying to use openOCD and jtag-hs2 to download code to the board as instructed in the README. I have checked the physical connection and make sure it be correctly connected to the Zcu102. Does anyone know what could potentially cause this error and ways to fix it? @en-sc I would really appreciate it.
here is the error I got:
Here is what it shows when I run with -d3 flag