Open l1onog opened 2 months ago
From the log it seems you are using a version from https://github.com/riscv-collab/riscv-openocd/commit/ca7d88252633a5d452ee92e6f8f3eb20cadfb633 (Feb 27). Please, try to use a more recent version. There were recent changes in DM examination related code. This would help me with diagnosing the issue a lot. Also, could you please attach a log in a file / zip archive. The conversation will get flooded with logs otherwise.
hi, @en-sc , I have used the latest version of openocd, and this is my result. d3.txt
@l1onog, looking at the logs it may be a different issue. Please, check if #1061 fixes it.
hi, @en-sc, I appreciate your suggestion, but it seems like it won’t resolve my issue.
new_d3.txt
I adjusted the 'set_command_timeout_sec' from 2 seconds to 240 seconds as suggested by the error message, but it still isn’t working."
@l1onog, looking at the logs it may be a different issue. Please, check if #1061 fixes it.
hi, @en-sc , I tried to replace the new JTAG-HS2, but it still reports an error, this is the exact error report, d3-2024-05-07.txt how do I actually fix it? What is the problem?
@l1onog, in the log you have attached it can be observed that:
dtmcs
is read successfully:
Debug: 97 6 riscv.c:1725 riscv_examine(): [riscv.cpu] Starting examination
Debug: 98 6 riscv.c:406 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1c71
Debug: 99 6 riscv.c:1739 riscv_examine(): [riscv.cpu] dtmcontrol=0x1c71
Debug: 100 6 riscv.c:1741 riscv_examine(): [riscv.cpu] version=0x1
dmcontrol
register does not succeed and returns busy for 2 minutes.
Debug: 109 7 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 0i
Debug: 110 7 riscv-013.c:492 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 111 7 riscv-013.c:481 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 112 7 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 1i
...
Debug: 562 124197 riscv-013.c:415 riscv_decode_dmi_scan(): 41b r 00000000 @10 -> b 00000000 @10; 11019046i
Debug: 563 124197 riscv-013.c:492 increase_dmi_busy_delay(): [riscv.cpu] dtmcs_idle=1, dmi_busy_delay=12120951, ac_busy_delay=0
Debug: 564 124199 riscv-013.c:481 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Error: 565 124199 riscv-013.c:694 dmi_op(): [riscv.cpu] DMI operation didn't complete in 120 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec.
I can see the following reasons for such behavior:
0x0
. This would indicate an issue with the Debug Module / Debug Message Interface you are using, since the spec requires [3.1. Debug Module Interface (DMI)]:
The bottom of the address space is used for the first (and usually only) DM Please, verify this is not the case with your provider of Debug Module / Debug Message Interface implemetation.
dmstatus
can not be read while dmstatus.dmactive
is low. Here I would also need further information about your DM implementation -- which version of RISC-V Debug Spec it supports (v0.13 or v1.0)? The specification is obscure in what is required from the DM when dmstatus.dmactive
is low and there is an issue described here: https://github.com/riscv/riscv-debug-spec/issues/1021Hi, @en-sc , Thank you for your kind reply, the version of RISCV debugging I am using is 0.13. Also, if it is my debugging module that is causing the problem, how can I fix it?
Also, if it is my debugging module that is causing the problem, how can I fix it?
By modifying the HDL code for the FPGA implementation of your RISC-V. But that's moot until such time as the root cause of your issues has been identified.
I implemented RISCV SoC on a Zcu102 fpga. I am trying to use openOCD and jtag-hs2 to download code to the board as instructed in the README. Does anyone know what could potentially cause this error and ways to fix it? @en-sc I would really appreciate it.
Here is what it shows when I run with -d3 flag:
Also, the contents of my cfg file: