search

riscv-collab / riscv-openocd

Fork of OpenOCD that has RISC-V support
Other
438 stars 319 forks source link

riscv openocd tests don't work with unavailable harts #359

Closed bluewww closed 4 years ago

bluewww commented 5 years ago

My (test)system has hartid=0 unavailable, hartid=1 first existing hart, hartid=2,3,4... nonexistent as allowed by the debug spec v0.13.1.

See p.10

Systems with very large number of harts may permanently disable some during manufacturing, leaving holes in the otherwise continuous hart index space. In order to let the debugger discover all harts, they must show up as unavailable even if there is no chance of them ever becoming available.

This happens when I try to run the tests (with -rtos)

Debug: 222 439 core.c:1190 jtag_validate_ircapture(): IR capture validation scan
Debug: 223 481 core.c:1248 jtag_validate_ircapture(): riscv.cpu: IR capture 0x05
Debug: 224 481 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_dap init
Debug: 225 481 command.c:143 script_debug(): command - ocd_dap ocd_dap init
Debug: 227 481 arm_dap.c:105 dap_init_all(): Initializing all DAPs ...
Debug: 228 481 openocd.c:159 handle_init_command(): Examining targets...
Debug: 229 481 target.c:1591 target_call_event_callbacks(): target event 17 (examine-start) for core 0
Debug: 230 481 riscv.c:785 riscv_examine(): riscv_examine()
Debug: 231 524 riscv.c:227 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 232 524 riscv.c:795 riscv_examine(): dtmcontrol=0x1071
Debug: 233 524 riscv.c:797 riscv_examine():   version=0x1
Debug: 234 524 riscv-013.c:1604 init_target(): init
Debug: 235 569 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 236 569 riscv-013.c:1370 examine(): dtmcontrol=0x1071
Debug: 237 569 riscv-013.c:1371 examine():   dmireset=0
Debug: 238 569 riscv-013.c:1372 examine():   idle=1
Debug: 239 569 riscv-013.c:1373 examine():   dmistat=0
Debug: 240 569 riscv-013.c:1374 examine():   abits=7
Debug: 241 569 riscv-013.c:1375 examine():   version=1
Debug: 242 614 riscv-013.c:379 scan(): 41b 0i w 00000000 @10 -> + 00000000 @00
Debug: 243 655 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 00000000 @10
Debug: 244 698 riscv-013.c:379 scan(): 41b 0i w 00000001 @10 -> + 00000000 @10
Debug: 245 698 riscv-013.c:390 scan():  dmactive -> 
Debug: 246 739 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 00000001 @10
Debug: 247 739 riscv-013.c:390 scan():  ->  dmactive
Debug: 248 782 riscv-013.c:379 scan(): 41b 0i w 03ffffc1 @10 -> + 00000000 @10
Debug: 249 782 riscv-013.c:390 scan():  hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 250 823 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 03ffffc1 @10
Debug: 251 823 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 252 866 riscv-013.c:379 scan(): 41b 0i r 00000000 @10 -> + 00000000 @10
Debug: 253 907 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> b 00000000 @10
Debug: 254 907 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 255 950 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 256 993 riscv-013.c:379 scan(): 41b 1i - 00000000 @10 -> + 03ffffc1 @10
Debug: 257 993 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 258 1036 riscv-013.c:379 scan(): 41b 1i r 00000000 @11 -> + 00000000 @10
Debug: 259 1077 riscv-013.c:379 scan(): 41b 1i - 00000000 @11 -> b 00000000 @11
Debug: 260 1077 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 261 1120 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 262 1163 riscv-013.c:379 scan(): 41b 2i - 00000000 @11 -> + 000ccc82 @11
Debug: 263 1163 riscv-013.c:390 scan():  ->  allhavereset anyhavereset allnonexistent anynonexistent allrunning anyrunning authenticated version=2
Debug: 264 1163 riscv-013.c:1413 examine(): dmstatus:  0x000ccc82
Debug: 265 1163 riscv-013.c:1429 examine(): hartsellen=20
Debug: 266 1206 riscv-013.c:379 scan(): 41b 2i r 00000000 @12 -> + 00000000 @11
Debug: 267 1247 riscv-013.c:379 scan(): 41b 2i - 00000000 @12 -> b 00000000 @12
Debug: 268 1247 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 269 1290 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 270 1333 riscv-013.c:379 scan(): 41b 3i - 00000000 @12 -> + 00000000 @12
Debug: 271 1376 riscv-013.c:379 scan(): 41b 3i r 00000000 @38 -> + 00000000 @12
Debug: 272 1417 riscv-013.c:379 scan(): 41b 3i - 00000000 @38 -> b 00000000 @38
Debug: 273 1417 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 274 1460 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 275 1503 riscv-013.c:379 scan(): 41b 4i - 00000000 @38 -> + 20040404 @38
Debug: 276 1503 riscv-013.c:390 scan():  ->  sbaccess=2 sbasize=32 sbaccess32
Debug: 277 1546 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @38
Debug: 278 1588 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 279 1588 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Info : 280 1588 riscv-013.c:1460 examine(): datacount=2 progbufsize=8
Info : 281 1588 riscv-013.c:1478 examine(): coreid=0 hart=0
Debug: 282 1631 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @16
Debug: 283 1673 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 03ffffc1 @10
Debug: 284 1673 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 285 1716 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 286 1716 riscv-013.c:390 scan():  dmactive -> 
Debug: 287 1758 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 288 1758 riscv-013.c:390 scan():  ->  dmactive
Debug: 289 1801 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 290 1843 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 291 1843 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Info : 292 1843 riscv-013.c:1490 examine(): anynonexistent=0 anyunavail=1
Info : 293 1843 riscv-013.c:1478 examine(): coreid=0 hart=1
Debug: 294 1886 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 295 1928 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 296 1928 riscv-013.c:390 scan():  ->  dmactive
Debug: 297 1971 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 298 1971 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 299 2013 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 300 2013 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 301 2056 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 302 2098 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 000c0c82 @11
Debug: 303 2098 riscv-013.c:390 scan():  ->  allhavereset anyhavereset allrunning anyrunning authenticated version=2
Info : 304 2098 riscv-013.c:1490 examine(): anynonexistent=0 anyunavail=0
Debug: 305 2141 riscv-013.c:379 scan(): 41b 4i w 10010001 @10 -> + 00000000 @11
Debug: 306 2141 riscv-013.c:390 scan():  hartsello=1 dmactive ackhavereset -> 
Debug: 307 2183 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 10010001 @10
Debug: 308 2183 riscv-013.c:390 scan():  ->  hartsello=1 dmactive ackhavereset
Debug: 309 2226 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 310 2268 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000c82 @11
Debug: 311 2268 riscv-013.c:390 scan():  ->  allrunning anyrunning authenticated version=2
Debug: 312 2268 riscv-013.c:2897 riscv013_halt_current_hart(): halting hart 1
Debug: 313 2311 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 314 2353 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000c82 @11
Debug: 315 2353 riscv-013.c:390 scan():  ->  allrunning anyrunning authenticated version=2
Debug: 316 2396 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 317 2438 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 318 2438 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 319 2481 riscv-013.c:379 scan(): 41b 4i w 80010001 @10 -> + 00000000 @10
Debug: 320 2481 riscv-013.c:390 scan(): haltreq hartsello=1 dmactive -> 
Debug: 321 2524 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 80010001 @10
Debug: 322 2524 riscv-013.c:390 scan():  -> haltreq hartsello=1 dmactive
Debug: 323 2573 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 324 2618 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 325 2618 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 326 2667 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 327 2711 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 328 2711 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 329 2760 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @11
Debug: 330 2760 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 331 2804 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 332 2804 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 333 2804 riscv-013.c:729 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 334 2853 riscv-013.c:379 scan(): 41b 4i w 00321008 @17 -> + 00000000 @10
Debug: 335 2897 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00321008 @17
Debug: 336 2946 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 337 2990 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000202 @16
Debug: 338 2990 riscv-013.c:390 scan():  ->  progbufsize=8 cmderr=2 datacount=2
Debug: 339 2990 riscv-013.c:744 execute_abstract_command(): command 0x321008 failed; abstractcs=0x8000202
Debug: 340 3039 riscv-013.c:379 scan(): 41b 4i w 00000200 @16 -> + 00000000 @16
Debug: 341 3039 riscv-013.c:390 scan():  cmderr=2 -> 
Debug: 342 3084 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 00000200 @16
Debug: 343 3084 riscv-013.c:390 scan():  ->  cmderr=2
Info : 344 3084 riscv-013.c:1519 examine(): DETERMINING XLEN=32 for HART=1
Debug: 345 3084 riscv-013.c:729 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 346 3133 riscv-013.c:379 scan(): 41b 4i w 00220301 @17 -> + 00000000 @16
Debug: 347 3177 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00220301 @17
Debug: 348 3226 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 349 3270 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 350 3270 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Debug: 351 3319 riscv-013.c:379 scan(): 41b 4i r 00000000 @04 -> + 00000000 @16
Debug: 352 3364 riscv-013.c:379 scan(): 41b 4i - 00000000 @04 -> + 00000000 @04
Debug: 353 3364 riscv-013.c:1325 register_read_direct(): {1} reg[0x342] = 0x0
Debug: 354 3364 riscv.c:2525 riscv_init_registers(): create register cache for 4162 registers
Debug: 355 3364 riscv-013.c:1532 examine():  hart 1: XLEN=32, misa=0x0
Debug: 356 3364 riscv-013.c:3446 riscv013_step_or_resume_current_hart(): resuming hart 1 (for step?=0)
Debug: 357 3414 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @04
Debug: 358 3458 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 359 3458 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 360 3458 log.c:409 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (3458). This may cause trouble with GDB connections.
Debug: 362 3458 program.c:33 riscv_program_write(): 0x7ffc65601c80: debug_buffer[00] = DASM(0x0000100f)
Debug: 363 3507 riscv-013.c:379 scan(): 41b 4i w 0000100f @20 -> + 00000000 @11
Debug: 364 3551 riscv-013.c:379 scan(): 41b 4i - 00000000 @20 -> + 0000100f @20
Debug: 365 3551 program.c:33 riscv_program_write(): 0x7ffc65601c80: debug_buffer[01] = DASM(0x0000000f)
Debug: 366 3600 riscv-013.c:379 scan(): 41b 4i w 0000000f @21 -> + 00000000 @20
Debug: 367 3647 riscv-013.c:379 scan(): 41b 4i - 00000000 @21 -> + 0000000f @21
Debug: 368 3647 program.c:33 riscv_program_write(): 0x7ffc65601c80: debug_buffer[02] = DASM(0x00100073)
Debug: 369 3701 riscv-013.c:379 scan(): 41b 4i w 00100073 @22 -> + 00000000 @21
Debug: 370 3748 riscv-013.c:379 scan(): 41b 4i - 00000000 @22 -> + 00100073 @22
Debug: 371 3748 riscv-013.c:729 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 372 3802 riscv-013.c:379 scan(): 41b 4i w 00241000 @17 -> + 00000000 @22
Debug: 373 3848 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00241000 @17
Debug: 374 3902 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 375 3949 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 376 3949 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Debug: 377 3949 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 378 4003 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @16
Debug: 379 4050 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 380 4050 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 381 4104 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 382 4104 riscv-013.c:390 scan():  dmactive -> 
Debug: 383 4151 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 384 4151 riscv-013.c:390 scan():  ->  dmactive
openocd: src/target/riscv/riscv.c:2124: riscv_xlen_of_hart: Assertion `r->xlen[hartid] != -1' failed.
Debug: 385 4151 server.c:609 sig_handler(): Terminating on Signal 6
Aborted

Working around that issue by forcing xlen=32. I get:

Debug: 228 480 openocd.c:159 handle_init_command(): Examining targets...
Debug: 229 480 target.c:1591 target_call_event_callbacks(): target event 17 (examine-start) for core 0
Debug: 230 480 riscv.c:785 riscv_examine(): riscv_examine()
Debug: 231 523 riscv.c:227 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 232 523 riscv.c:795 riscv_examine(): dtmcontrol=0x1071
Debug: 233 523 riscv.c:797 riscv_examine():   version=0x1
Debug: 234 523 riscv-013.c:1604 init_target(): init
Debug: 235 568 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 236 568 riscv-013.c:1370 examine(): dtmcontrol=0x1071
Debug: 237 568 riscv-013.c:1371 examine():   dmireset=0
Debug: 238 568 riscv-013.c:1372 examine():   idle=1
Debug: 239 568 riscv-013.c:1373 examine():   dmistat=0
Debug: 240 568 riscv-013.c:1374 examine():   abits=7
Debug: 241 568 riscv-013.c:1375 examine():   version=1
Debug: 242 613 riscv-013.c:379 scan(): 41b 0i w 00000000 @10 -> + 00000000 @00
Debug: 243 654 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 00000000 @10
Debug: 244 697 riscv-013.c:379 scan(): 41b 0i w 00000001 @10 -> + 00000000 @10
Debug: 245 697 riscv-013.c:390 scan():  dmactive -> 
Debug: 246 738 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 00000001 @10
Debug: 247 738 riscv-013.c:390 scan():  ->  dmactive
Debug: 248 781 riscv-013.c:379 scan(): 41b 0i w 03ffffc1 @10 -> + 00000000 @10
Debug: 249 781 riscv-013.c:390 scan():  hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 250 822 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> + 03ffffc1 @10
Debug: 251 822 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 252 865 riscv-013.c:379 scan(): 41b 0i r 00000000 @10 -> + 00000000 @10
Debug: 253 906 riscv-013.c:379 scan(): 41b 0i - 00000000 @10 -> b 00000000 @10
Debug: 254 906 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 255 949 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 256 992 riscv-013.c:379 scan(): 41b 1i - 00000000 @10 -> + 03ffffc1 @10
Debug: 257 992 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 258 1036 riscv-013.c:379 scan(): 41b 1i r 00000000 @11 -> + 00000000 @10
Debug: 259 1077 riscv-013.c:379 scan(): 41b 1i - 00000000 @11 -> b 00000000 @11
Debug: 260 1077 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 261 1120 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 262 1163 riscv-013.c:379 scan(): 41b 2i - 00000000 @11 -> + 000ccc82 @11
Debug: 263 1163 riscv-013.c:390 scan():  ->  allhavereset anyhavereset allnonexistent anynonexistent allrunning anyrunning authenticated version=2
Debug: 264 1163 riscv-013.c:1413 examine(): dmstatus:  0x000ccc82
Debug: 265 1163 riscv-013.c:1429 examine(): hartsellen=20
Debug: 266 1206 riscv-013.c:379 scan(): 41b 2i r 00000000 @12 -> + 00000000 @11
Debug: 267 1247 riscv-013.c:379 scan(): 41b 2i - 00000000 @12 -> b 00000000 @12
Debug: 268 1247 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 269 1290 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 270 1333 riscv-013.c:379 scan(): 41b 3i - 00000000 @12 -> + 00000000 @12
Debug: 271 1377 riscv-013.c:379 scan(): 41b 3i r 00000000 @38 -> + 00000000 @12
Debug: 272 1418 riscv-013.c:379 scan(): 41b 3i - 00000000 @38 -> b 00000000 @38
Debug: 273 1418 riscv-013.c:438 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 274 1461 riscv-013.c:427 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 275 1504 riscv-013.c:379 scan(): 41b 4i - 00000000 @38 -> + 20040404 @38
Debug: 276 1504 riscv-013.c:390 scan():  ->  sbaccess=2 sbasize=32 sbaccess32
Debug: 277 1547 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @38
Debug: 278 1589 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 279 1589 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Info : 280 1589 riscv-013.c:1460 examine(): datacount=2 progbufsize=8
Info : 281 1589 riscv-013.c:1478 examine(): coreid=0 hart=0
Debug: 282 1633 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @16
Debug: 283 1675 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 03ffffc1 @10
Debug: 284 1675 riscv-013.c:390 scan():  ->  hartselhi=1023 hartsello=1023 dmactive
Debug: 285 1719 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 286 1719 riscv-013.c:390 scan():  dmactive -> 
Debug: 287 1761 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 288 1761 riscv-013.c:390 scan():  ->  dmactive
Debug: 289 1804 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 290 1846 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 291 1846 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Info : 292 1846 riscv-013.c:1490 examine(): anynonexistent=0 anyunavail=1
Info : 293 1846 riscv-013.c:1478 examine(): coreid=0 hart=1
Debug: 294 1890 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 295 1932 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 296 1932 riscv-013.c:390 scan():  ->  dmactive
Debug: 297 1975 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 298 1975 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 299 2017 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 300 2017 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 301 2060 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 302 2102 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 000c0c82 @11
Debug: 303 2102 riscv-013.c:390 scan():  ->  allhavereset anyhavereset allrunning anyrunning authenticated version=2
Info : 304 2102 riscv-013.c:1490 examine(): anynonexistent=0 anyunavail=0
Debug: 305 2146 riscv-013.c:379 scan(): 41b 4i w 10010001 @10 -> + 00000000 @11
Debug: 306 2146 riscv-013.c:390 scan():  hartsello=1 dmactive ackhavereset -> 
Debug: 307 2188 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 10010001 @10
Debug: 308 2188 riscv-013.c:390 scan():  ->  hartsello=1 dmactive ackhavereset
Debug: 309 2231 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 310 2273 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000c82 @11
Debug: 311 2273 riscv-013.c:390 scan():  ->  allrunning anyrunning authenticated version=2
Debug: 312 2273 riscv-013.c:2897 riscv013_halt_current_hart(): halting hart 1
Debug: 313 2316 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 314 2358 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000c82 @11
Debug: 315 2358 riscv-013.c:390 scan():  ->  allrunning anyrunning authenticated version=2
Debug: 316 2401 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 317 2443 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 318 2443 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 319 2486 riscv-013.c:379 scan(): 41b 4i w 80010001 @10 -> + 00000000 @10
Debug: 320 2486 riscv-013.c:390 scan(): haltreq hartsello=1 dmactive -> 
Debug: 321 2529 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 80010001 @10
Debug: 322 2529 riscv-013.c:390 scan():  -> haltreq hartsello=1 dmactive
Debug: 323 2579 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 324 2623 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 325 2623 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 326 2672 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 327 2717 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 328 2717 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 329 2766 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @11
Debug: 330 2766 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 331 2810 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 332 2810 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 333 2810 riscv-013.c:729 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 334 2859 riscv-013.c:379 scan(): 41b 4i w 00321008 @17 -> + 00000000 @10
Debug: 335 2903 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00321008 @17
Debug: 336 2952 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 337 2996 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000202 @16
Debug: 338 2996 riscv-013.c:390 scan():  ->  progbufsize=8 cmderr=2 datacount=2
Debug: 339 2996 riscv-013.c:744 execute_abstract_command(): command 0x321008 failed; abstractcs=0x8000202
Debug: 340 3045 riscv-013.c:379 scan(): 41b 4i w 00000200 @16 -> + 00000000 @16
Debug: 341 3045 riscv-013.c:390 scan():  cmderr=2 -> 
Debug: 342 3089 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 00000200 @16
Debug: 343 3089 riscv-013.c:390 scan():  ->  cmderr=2
Info : 344 3089 riscv-013.c:1519 examine(): DETERMINING XLEN=32 for HART=1
Debug: 345 3089 riscv-013.c:729 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 346 3138 riscv-013.c:379 scan(): 41b 4i w 00220301 @17 -> + 00000000 @16
Debug: 347 3182 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00220301 @17
Debug: 348 3231 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 349 3275 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 350 3275 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Debug: 351 3324 riscv-013.c:379 scan(): 41b 4i r 00000000 @04 -> + 00000000 @16
Debug: 352 3368 riscv-013.c:379 scan(): 41b 4i - 00000000 @04 -> + 00000000 @04
Debug: 353 3368 riscv-013.c:1325 register_read_direct(): {1} reg[0x342] = 0x0
Debug: 354 3368 riscv.c:2525 riscv_init_registers(): create register cache for 4162 registers
Debug: 355 3368 riscv-013.c:1532 examine():  hart 1: XLEN=32, misa=0x0
Debug: 356 3368 riscv-013.c:3446 riscv013_step_or_resume_current_hart(): resuming hart 1 (for step?=0)
Debug: 357 3418 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @04
Debug: 358 3462 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00000382 @11
Debug: 359 3462 riscv-013.c:390 scan():  ->  allhalted anyhalted authenticated version=2
Debug: 360 3462 log.c:409 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (3462). This may cause trouble with GDB connections.
Debug: 362 3462 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[00] = DASM(0x0000100f)
Debug: 363 3511 riscv-013.c:379 scan(): 41b 4i w 0000100f @20 -> + 00000000 @11
Debug: 364 3556 riscv-013.c:379 scan(): 41b 4i - 00000000 @20 -> + 0000100f @20
Debug: 365 3556 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[01] = DASM(0x0000000f)
Debug: 366 3605 riscv-013.c:379 scan(): 41b 4i w 0000000f @21 -> + 00000000 @20
Debug: 367 3650 riscv-013.c:379 scan(): 41b 4i - 00000000 @21 -> + 0000000f @21
Debug: 368 3650 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[02] = DASM(0x00100073)
Debug: 369 3699 riscv-013.c:379 scan(): 41b 4i w 00100073 @22 -> + 00000000 @21
Debug: 370 3743 riscv-013.c:379 scan(): 41b 4i - 00000000 @22 -> + 00100073 @22
Debug: 371 3743 riscv-013.c:729 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 372 3792 riscv-013.c:379 scan(): 41b 4i w 00241000 @17 -> + 00000000 @22
Debug: 373 3836 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00241000 @17
Debug: 374 3885 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 375 3929 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 376 3929 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Debug: 377 3929 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 378 3978 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @16
Debug: 379 4022 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 380 4022 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 381 4071 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 382 4071 riscv-013.c:390 scan():  dmactive -> 
Debug: 383 4115 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 384 4115 riscv-013.c:390 scan():  ->  dmactive
Error: 385 4115 program.c:153 riscv_program_insert(): Unable to insert instruction:
Error: 386 4115 program.c:154 riscv_program_insert():   instruction_count=0
Error: 387 4115 program.c:155 riscv_program_insert():   buffer size      =0
Error: 388 4115 program.c:153 riscv_program_insert(): Unable to insert instruction:
Error: 389 4115 program.c:154 riscv_program_insert():   instruction_count=0
Error: 390 4115 program.c:155 riscv_program_insert():   buffer size      =0
Error: 392 4115 program.c:153 riscv_program_insert(): Unable to insert instruction:
Error: 393 4115 program.c:154 riscv_program_insert():   instruction_count=0
Error: 394 4115 program.c:155 riscv_program_insert():   buffer size      =0
Error: 395 4115 program.c:57 riscv_program_exec(): Unable to write ebreak
Debug: 396 4115 riscv-013.c:1828 execute_fence(): Unable to execute fence on hart 0
Debug: 397 4115 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 398 4164 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @10
Debug: 399 4208 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 400 4208 riscv-013.c:390 scan():  ->  dmactive
Debug: 401 4257 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 402 4257 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 403 4302 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 404 4302 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 405 4302 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[00] = DASM(0x0000100f)
Debug: 406 4351 riscv-013.c:379 scan(): 41b 4i w 0000100f @20 -> + 00000000 @10
Debug: 407 4395 riscv-013.c:379 scan(): 41b 4i - 00000000 @20 -> + 0000100f @20
Debug: 408 4395 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[01] = DASM(0x0000000f)
Debug: 409 4444 riscv-013.c:379 scan(): 41b 4i w 0000000f @21 -> + 00000000 @20
Debug: 410 4489 riscv-013.c:379 scan(): 41b 4i - 00000000 @21 -> + 0000000f @21
Debug: 411 4489 program.c:33 riscv_program_write(): 0x7ffc9a694170: debug_buffer[02] = DASM(0x00100073)
Debug: 412 4538 riscv-013.c:379 scan(): 41b 4i w 00100073 @22 -> + 00000000 @21
Debug: 413 4582 riscv-013.c:379 scan(): 41b 4i - 00000000 @22 -> + 00100073 @22
Debug: 414 4582 riscv-013.c:729 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 415 4631 riscv-013.c:379 scan(): 41b 4i w 00241000 @17 -> + 00000000 @22
Debug: 416 4675 riscv-013.c:379 scan(): 41b 4i - 00000000 @17 -> + 00241000 @17
Debug: 417 4724 riscv-013.c:379 scan(): 41b 4i r 00000000 @16 -> + 00000000 @17
Debug: 418 4768 riscv-013.c:379 scan(): 41b 4i - 00000000 @16 -> + 08000002 @16
Debug: 419 4768 riscv-013.c:390 scan():  ->  progbufsize=8 datacount=2
Debug: 420 4768 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 1
Debug: 421 4817 riscv-013.c:379 scan(): 41b 4i w 40010001 @10 -> + 00000000 @16
Debug: 422 4817 riscv-013.c:390 scan():  resumereq hartsello=1 dmactive -> 
Debug: 423 4861 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 40010001 @10
Debug: 424 4861 riscv-013.c:390 scan():  ->  resumereq hartsello=1 dmactive
Debug: 425 4905 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 426 4947 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 427 4947 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 428 4990 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @11
Debug: 429 4990 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 430 5032 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 431 5032 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Info : 432 5032 riscv-013.c:1478 examine(): coreid=0 hart=2
Debug: 433 5075 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @10
Debug: 434 5117 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 435 5117 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 436 5160 riscv-013.c:379 scan(): 41b 4i w 00020001 @10 -> + 00000000 @10
Debug: 437 5160 riscv-013.c:390 scan():  hartsello=2 dmactive -> 
Debug: 438 5202 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00020001 @10
Debug: 439 5202 riscv-013.c:390 scan():  ->  hartsello=2 dmactive
Debug: 440 5245 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 441 5287 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 0000f082 @11
Debug: 442 5287 riscv-013.c:390 scan():  ->  allnonexistent anynonexistent allunavail anyunavail authenticated version=2
Info : 443 5287 riscv-013.c:1490 examine(): anynonexistent=1 anyunavail=1
Debug: 444 5287 riscv-013.c:1538 examine(): Enumerated 2 harts
Debug: 445 5287 riscv_debug.c:39 riscv_update_threads(): Updating the RISC-V Hart List
Debug: 446 5287 riscv_debug.c:50 riscv_update_threads():   Setting up Hart 0
Debug: 447 5287 riscv_debug.c:50 riscv_update_threads():   Setting up Hart 1
Info : 448 5287 riscv-013.c:1554 examine(): Examined RISC-V core; found 2 harts
Info : 449 5287 riscv-013.c:1558 examine():  hart 0: XLEN=-1, misa=0x0
Info : 450 5287 riscv-013.c:1558 examine():  hart 1: XLEN=32, misa=0x0
Debug: 451 5287 target.c:1591 target_call_event_callbacks(): target event 18 (examine-end) for core 0
Debug: 452 5287 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 453 5287 command.c:143 script_debug(): command - ocd_flash ocd_flash init
Debug: 454 5287 log.c:409 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (1172). This may cause trouble with GDB connections.
Debug: 456 5287 riscv.c:1190 riscv_openocd_poll(): polling all harts
Debug: 457 5287 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 2
Debug: 458 5330 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 459 5372 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00020001 @10
Debug: 460 5372 riscv-013.c:390 scan():  ->  hartsello=2 dmactive
Debug: 461 5415 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 462 5415 riscv-013.c:390 scan():  dmactive -> 
Debug: 463 5457 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 464 5457 riscv-013.c:390 scan():  ->  dmactive
Debug: 465 5457 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 466 5457 riscv.c:1145 riscv_poll_hart(): polling hart 0, target->state=0
Debug: 467 5500 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 468 5542 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 469 5542 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 470 5542 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 471 5542 riscv.c:1155 riscv_poll_hart():   triggered running
Debug: 472 5542 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 473 5585 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 474 5627 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 475 5627 riscv-013.c:390 scan():  ->  dmactive
Debug: 476 5670 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 477 5670 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 478 5712 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 479 5712 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 480 5712 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 481 5712 riscv.c:1145 riscv_poll_hart(): polling hart 1, target->state=1
Debug: 482 5755 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 483 5797 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 484 5797 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 485 5797 riscv.c:1208 riscv_openocd_poll():   no harts just halted, target->state=1
Debug: 487 5797 tcl.c:1225 handle_flash_init_command(): Initializing flash devices...
Debug: 488 5797 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 489 5797 command.c:143 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 491 5797 riscv.c:1190 riscv_openocd_poll(): polling all harts
Debug: 492 5797 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 493 5840 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 494 5882 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 495 5882 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 496 5925 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 497 5925 riscv-013.c:390 scan():  dmactive -> 
Debug: 498 5967 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 499 5967 riscv-013.c:390 scan():  ->  dmactive
Debug: 500 5967 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 501 5967 riscv.c:1145 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 502 6010 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 503 6052 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 504 6052 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 505 6052 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 506 6052 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 507 6095 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 508 6137 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 509 6137 riscv-013.c:390 scan():  ->  dmactive
Debug: 510 6180 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 511 6180 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 512 6222 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 513 6222 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 514 6222 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 515 6222 riscv.c:1145 riscv_poll_hart(): polling hart 1, target->state=1
Debug: 516 6265 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 517 6307 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 518 6307 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 519 6307 riscv.c:1208 riscv_openocd_poll():   no harts just halted, target->state=1
Debug: 521 6307 mflash.c:1377 handle_mflash_init_command(): Initializing mflash devices...
Debug: 522 6307 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 523 6307 command.c:143 script_debug(): command - ocd_nand ocd_nand init
Debug: 525 6307 riscv.c:1190 riscv_openocd_poll(): polling all harts
Debug: 526 6307 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 527 6350 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 528 6392 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 529 6392 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 530 6435 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 531 6435 riscv-013.c:390 scan():  dmactive -> 
Debug: 532 6477 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 533 6477 riscv-013.c:390 scan():  ->  dmactive
Debug: 534 6477 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 535 6477 riscv.c:1145 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 536 6520 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 537 6562 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 538 6562 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 539 6562 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 540 6562 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 541 6605 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 542 6647 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 543 6647 riscv-013.c:390 scan():  ->  dmactive
Debug: 544 6690 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 545 6690 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 546 6732 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 547 6732 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 548 6732 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 549 6732 riscv.c:1145 riscv_poll_hart(): polling hart 1, target->state=1
Debug: 550 6775 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 551 6817 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 552 6817 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 553 6817 riscv.c:1208 riscv_openocd_poll():   no harts just halted, target->state=1
Debug: 555 6817 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 556 6817 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 557 6817 command.c:143 script_debug(): command - ocd_pld ocd_pld init
Debug: 559 6817 riscv.c:1190 riscv_openocd_poll(): polling all harts
Debug: 560 6817 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 561 6860 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 562 6902 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 563 6902 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 564 6945 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 565 6945 riscv-013.c:390 scan():  dmactive -> 
Debug: 566 6987 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 567 6987 riscv-013.c:390 scan():  ->  dmactive
Debug: 568 6987 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 569 6987 riscv.c:1145 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 570 7030 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 571 7072 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 572 7072 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 573 7072 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 574 7072 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 575 7115 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 576 7157 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 577 7157 riscv-013.c:390 scan():  ->  dmactive
Debug: 578 7200 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 579 7200 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 580 7242 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 581 7242 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 582 7242 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 583 7242 riscv.c:1145 riscv_poll_hart(): polling hart 1, target->state=1
Debug: 584 7285 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 585 7327 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 586 7327 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 587 7327 riscv.c:1208 riscv_openocd_poll():   no harts just halted, target->state=1
Debug: 589 7327 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 590 7327 gdb_server.c:3412 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 591 7327 server.c:311 add_service(): Listening on port 3333 for gdb connections
Debug: 592 7327 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv test_compliance
Debug: 593 7327 command.c:143 script_debug(): command - ocd_riscv ocd_riscv test_compliance
Debug: 595 7327 riscv.c:1190 riscv_openocd_poll(): polling all harts
Debug: 596 7327 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 597 7370 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 598 7412 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 599 7412 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 600 7455 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 601 7455 riscv-013.c:390 scan():  dmactive -> 
Debug: 602 7497 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 603 7497 riscv-013.c:390 scan():  ->  dmactive
Debug: 604 7497 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 605 7497 riscv.c:1145 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 606 7540 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 607 7582 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 608 7582 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 609 7582 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 610 7582 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 1, was 0
Debug: 611 7625 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 612 7667 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 613 7667 riscv-013.c:390 scan():  ->  dmactive
Debug: 614 7710 riscv-013.c:379 scan(): 41b 4i w 00010001 @10 -> + 00000000 @10
Debug: 615 7710 riscv-013.c:390 scan():  hartsello=1 dmactive -> 
Debug: 616 7752 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00010001 @10
Debug: 617 7752 riscv-013.c:390 scan():  ->  hartsello=1 dmactive
Debug: 618 7752 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 619 7752 riscv.c:1145 riscv_poll_hart(): polling hart 1, target->state=1
Debug: 620 7795 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 621 7836 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00030c82 @11
Debug: 622 7836 riscv-013.c:390 scan():  ->  allresumeack anyresumeack allrunning anyrunning authenticated version=2
Debug: 623 7836 riscv.c:1208 riscv_openocd_poll():   no harts just halted, target->state=1
Info : 625 7836 riscv-013.c:3542 riscv013_test_compliance(): Testing Compliance against RISC-V Debug Spec v0.13
Debug: 626 7879 riscv-013.c:379 scan(): 41b 4i w 20000001 @10 -> + 00000000 @11
Debug: 627 7879 riscv-013.c:390 scan():  hartreset dmactive -> 
Debug: 628 7921 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 20000001 @10
Debug: 629 7921 riscv-013.c:390 scan():  ->  hartreset dmactive
Info : 630 7921 riscv-013.c:3566 riscv013_test_compliance(): PASSED test 0 (Regular calls must return ERROR_OK)

Debug: 631 7964 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 632 7964 riscv-013.c:390 scan():  dmactive -> 
Debug: 633 8006 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 634 8006 riscv-013.c:390 scan():  ->  dmactive
Info : 635 8006 riscv-013.c:3567 riscv013_test_compliance(): PASSED test 1 (Regular calls must return ERROR_OK)

Debug: 636 8049 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @10
Debug: 637 8091 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 638 8091 riscv-013.c:390 scan():  ->  dmactive
Info : 639 8091 riscv-013.c:3568 riscv013_test_compliance(): PASSED test 2 (Regular calls must return ERROR_OK)

Info : 640 8091 riscv-013.c:3570 riscv013_test_compliance(): PASSED test 3 (DMCONTROL.hartreset can be 0 or RW.)

Debug: 641 8134 riscv-013.c:379 scan(): 41b 4i w 04000001 @10 -> + 00000000 @10
Debug: 642 8134 riscv-013.c:390 scan():  hasel dmactive -> 
Debug: 643 8176 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 04000001 @10
Debug: 644 8176 riscv-013.c:390 scan():  ->  hasel dmactive
Info : 645 8176 riscv-013.c:3573 riscv013_test_compliance(): PASSED test 4 (Regular calls must return ERROR_OK)

Debug: 646 8219 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 647 8219 riscv-013.c:390 scan():  dmactive -> 
Debug: 648 8261 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 649 8261 riscv-013.c:390 scan():  ->  dmactive
Info : 650 8261 riscv-013.c:3574 riscv013_test_compliance(): PASSED test 5 (Regular calls must return ERROR_OK)

Debug: 651 8304 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @10
Debug: 652 8346 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 653 8346 riscv-013.c:390 scan():  ->  dmactive
Info : 654 8346 riscv-013.c:3575 riscv013_test_compliance(): PASSED test 6 (Regular calls must return ERROR_OK)

Info : 655 8346 riscv-013.c:3577 riscv013_test_compliance(): PASSED test 7 (DMCONTROL.hasel can be 0 or RW.)

Debug: 656 8346 riscv.c:2030 riscv_halt_one_hart(): halting hart 0
Debug: 657 8346 riscv.c:2144 riscv_set_current_hartid(): setting hartid to 0, was 1
Debug: 658 8389 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @10
Debug: 659 8431 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 660 8431 riscv-013.c:390 scan():  ->  dmactive
Debug: 661 8474 riscv-013.c:379 scan(): 41b 4i w 00000001 @10 -> + 00000000 @10
Debug: 662 8474 riscv-013.c:390 scan():  dmactive -> 
Debug: 663 8516 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 664 8516 riscv-013.c:390 scan():  ->  dmactive
Debug: 665 8516 riscv.c:2160 riscv_invalidate_register_cache(): [0]
Debug: 666 8559 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 667 8601 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 668 8601 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 669 8601 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 670 8601 riscv-013.c:2897 riscv013_halt_current_hart(): halting hart 0
Debug: 671 8644 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 672 8685 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 673 8685 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 674 8685 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 675 8728 riscv-013.c:379 scan(): 41b 4i r 00000000 @10 -> + 00000000 @11
Debug: 676 8770 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 00000001 @10
Debug: 677 8770 riscv-013.c:390 scan():  ->  dmactive
Debug: 678 8813 riscv-013.c:379 scan(): 41b 4i w 80000001 @10 -> + 00000000 @10
Debug: 679 8813 riscv-013.c:390 scan(): haltreq dmactive -> 
Debug: 680 8855 riscv-013.c:379 scan(): 41b 4i - 00000000 @10 -> + 80000001 @10
Debug: 681 8855 riscv-013.c:390 scan():  -> haltreq dmactive
Debug: 682 8898 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @10
Debug: 683 8940 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 684 8940 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 685 8940 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 686 8983 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 687 9025 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 688 9025 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 689 9025 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 690 9068 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 691 9110 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 692 9110 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 693 9110 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 694 9153 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 695 9195 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 696 9195 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 697 9195 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 698 9238 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 699 9279 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 700 9279 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 701 9279 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 702 9322 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 703 9364 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 704 9364 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 705 9364 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 706 9407 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 707 9449 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 708 9449 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 709 9449 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 710 9492 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 711 9534 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 712 9534 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 713 9534 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
Debug: 714 9577 riscv-013.c:379 scan(): 41b 4i r 00000000 @11 -> + 00000000 @11
Debug: 715 9619 riscv-013.c:379 scan(): 41b 4i - 00000000 @11 -> + 00003082 @11
Debug: 716 9619 riscv-013.c:390 scan():  ->  allunavail anyunavail authenticated version=2
Error: 717 9619 riscv-013.c:2961 riscv013_is_halted(): Hart 0 is unavailable.
[...]

whereas the last errors are being repeated.

timsifive commented 5 years ago

OpenOCD currently has no concept of debug index to hart id mapping. It assumes they're equal and, as you discovered, that they're continuous starting at 0. This is a problem and needs to be fixed. I have a bit of a backlog, however, and can't tell when I'll get to it.

If you want to take a look at this code, I would think the first step is to mess with riscv-013.c examine() so that it checks for the unavailable bits and doesn't terminate discovery. Then you have the problem that hart index 0 should be ignored altogether.

You may be able to work around this problem by explicitly specifying the hart id in the OpenOCD configuration file. See e.g.https://github.com/riscv/riscv-tests/blob/master/debug/targets/RISC-V/spike-2.cfg which configures core ID 0 and 1. I'm not sure if anything is going to break if the numbers aren't contiguous.

bluewww commented 5 years ago

Don't you think we should establish a mapping between continuous "debug indices" to the existing harts in examine() and then go from there?

Another (imo ugly) way, is to establish a one to one correspondence between "debug indices" to hart id and then do the stuff of ignoring the corresponding harts. Infact currently I'm setting RISCV_MAX_HARTS to 1024 because in my setup, due to legacy reasons, the first available hart number might be as high as 992. This doesn't work for -rtos though.

timsifive commented 5 years ago

Yes, there should be a mapping from indices to harts.

Some day, when -rtos riscv can go away and everybody will use -rtos hwthread instead, then RISCV_MAX_HARTS can be gotten rid of altogether.

timsifive commented 4 years ago

This is a duplicate of #278.