Is there way to use openOCD with verilog CPU simulations?

[agrobman]

Does openOCD have a "verilog" target/driver for simulations?

[TommyMurphyTM1234]

You mean to connect openocd to a Verilog simulator and debug that? I'm pretty sure that it doesn't.

[mwachs5]

Yes you can, using either jtag_vpi or the remote-bitbang interface. There are instructions and useful files in github.com/chipsalliance/rocket-chip.

This assumes the thing you’re simulating has a real JTAG interface.

On Thu, Feb 6, 2020 at 6:15 AM Tommy Murphy notifications@github.com wrote:

You mean to connect openocd to a Verilog simulator and debug that? I'm pretty sure that it doesn't.

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/riscv/riscv-openocd/issues/446?email_source=notifications&email_token=AEIIAJFLQQJDD5MK4RBDULTRBQLP3A5CNFSM4KQ5NDXKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEK7LQZQ#issuecomment-582924390, or unsubscribe https://github.com/notifications/unsubscribe-auth/AEIIAJGAUDV5DCFG32DAR6DRBQLP3ANCNFSM4KQ5NDXA .

-- Megan A. Wachs VP of Engineering | SiFive, Inc 1875 South Grant Street Suite 600 San Mateo, CA 94402 megan@sifive.com

[TommyMurphyTM1234]

Apologies - I wasn't aware of those interfaces being relevant here.

[agrobman]

Megan, thanks a lot for the pointers, Could you, please, point to verilog part of the bitbang interface and some documentations for it? Thanks again Alex

[agrobman]

How do I compile/build the openOCD with the bitbang interface? what are the build options?

[TommyMurphyTM1234]

You mean remote bitbang?

configure .... --enable-remote-bitbang

https://github.com/riscv/riscv-openocd/blob/riscv/configure.ac#L356

[mwachs5]

Hi Alex, check out this readme section of the rocket-chip repo: https://github.com/chipsalliance/rocket-chip/blob/master/README.md#1-generating-the-remote-bit-bang-rbb-emulator

Sources:

https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/vsrc/SimJTAG.v and https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/csrc/SimJTAG.cc , https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/csrc/remote_bitbang.cc

On Tue, Mar 17, 2020 at 3:03 PM Tommy Murphy notifications@github.com wrote:

You mean remote bitbang?

configure .... --enable-remote-bitbang

https://github.com/riscv/riscv-openocd/blob/riscv/configure.ac#L356

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/riscv/riscv-openocd/issues/446#issuecomment-600322696, or unsubscribe https://github.com/notifications/unsubscribe-auth/AEIIAJDTHDX5CAWVIC3YSHDRH7XUXANCNFSM4KQ5NDXA .

-- Megan A. Wachs VP of Engineering | SiFive, Inc 1875 South Grant Street Suite 600 San Mateo, CA 94402 megan@sifive.com

[agrobman]

I need to co-simulate openOCD with CPU verilog model. Is this setup suitable for this?

[mwachs5]

Yes, this will let you connect with GDB + OpenOCD to a running verilog simulation, if you compile the C and V srcs into your simulation.

On Tue, Mar 17, 2020 at 3:07 PM agrobman notifications@github.com wrote:

I need to co-simulate openOCD with CPU verilog model. Is this setup suitable for this?

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/riscv/riscv-openocd/issues/446#issuecomment-600324057, or unsubscribe https://github.com/notifications/unsubscribe-auth/AEIIAJEUKV74XR6NXKLQFALRH7YDBANCNFSM4KQ5NDXA .

-- Megan A. Wachs VP of Engineering | SiFive, Inc 1875 South Grant Street Suite 600 San Mateo, CA 94402 megan@sifive.com

[agrobman]

Thanks a lot guys, I'm more HW/verilog person - know nothing about linux internals, program building and inter-processes communications. Hopefully the provided info will be enough for me to build something working :)

[agrobman]

got this:

... checking for LIBUSB1... no configure: WARNING: libusb-1.x not found, trying legacy libusb-0.1 as a fallback; consider installing libusb-1.x instead checking for LIBUSB0... yes checking for HIDAPI... no checking for HIDAPI... no checking for HIDAPI... no checking for LIBFTDI... no checking for LIBFTDI... no checking for LIBJAYLINK... no checking for environ in unistd.h and stdlib.h... yes configure: creating ./config.status config.status: error: cannot find input file: `Makefile.in'

Is this because of libusb1 ? Why do I need USB driver if I build bitbang?

[TommyMurphyTM1234]

As ever I'll suggest Liviu Ionescu's binary builds or his docker based build scripts as arguably the easiest and most predictable way to (cross) compile openocd (and all dependencies) for Windows (32 or 64 bit), Linux (32 or 64 bit) and MacOS.

• https://xpack.github.io/openocd/
• https://github.com/xpack-dev-tools/openocd-xpack/blob/xpack/README-BUILD.md
• https://github.com/xpack-dev-tools/openocd-xpack/blob/xpack/scripts/defs-source.sh#L43

[agrobman]

Hi,

How should I run the openocd with bitbang driver/CPU RTL? what are the command option/initialization scripts, etc. We just made connection, but looks like the openocd tries to detect availiable TAP controllers reads JTAG ID from our RTL and terminates with:

warn: There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! ...

[olofk]

@agrobman You can try jtag_vpi instead. There are instructions in the SweRVolf repo on how to run it against simulated models of SweRV EH1

[agrobman]

@olofk , we are already done with this task, thanks for advice

[hyperion009]

@agrobman I plan to do the same task as you. Could you provide some instructions , doc, or linker to some useful guides.

[TommyMurphyTM1234]

@agrobman I plan to do the same task as you. Could you provide some instructions , doc, or linker to some useful guides.

What exactly have you tried from the links posted earlier and what issues did you encounter?

[JanMatCodasip]

@hyperion009, there are at least two protocols supported in OpenOCD that allow to transmit the JTAG transactions over a TCP connection, e.g. towards the simulation:

• remote_bitbang
• jtag_vpi

For jtag_vpi, you can find a reusable example of the server-side side code (which should be integrated into your simulation) here: https://github.com/fjullien/jtag_vpi