Closed kingstone1927 closed 7 months ago
Hi kingstone1927,
This appears not to be an issue of OpenOCD. Current version of OpenOCD is known to work fine with SweRV. It is more likely a problem with SweRV integration into your design. Please continue the discussion in the SweRV repo, where you have better chance of getting advice for your problem: https://github.com/chipsalliance/Cores-SweRV/issues/
Few notes that may help you:
It appears that access to RISC-V debug module registers is not working for you.
The log shows it is possible to read DTMCS JTAG register but not DMI register. DMI access returns "all zeros":
Debug: 262 29 riscv-013.c:458 dtmcontrol_scan(): DTMCS: 0x0 -> 0x71
Debug: 263 29 riscv-013.c:1575 examine(): dtmcontrol=0x71
Debug: 264 29 riscv-013.c:1576 examine(): dmireset=0
Debug: 265 29 riscv-013.c:1577 examine(): idle=0
Debug: 266 29 riscv-013.c:1578 examine(): dmistat=0
Debug: 267 29 riscv-013.c:1579 examine(): abits=7
Debug: 268 29 riscv-013.c:1580 examine(): version=1
Debug: 269 29 riscv-013.c:264 get_dm(): [0] Allocating new DM
Debug: 270 30 riscv-013.c:404 scan(): 41b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 271 30 riscv-013.c:404 scan(): 41b - 00000000 @10 -> + 00000000 @00; 0i
Debug: 272 31 riscv-013.c:404 scan(): 41b w 00000001 @10 -> + 00000000 @00; 0i
Debug: 273 31 riscv-013.c:414 scan(): dmactive ->
Debug: 274 32 riscv-013.c:404 scan(): 41b - 00000000 @10 -> + 00000000 @00; 0i
Debug: 275 33 riscv-013.c:404 scan(): 41b w 07ffffc1 @10 -> + 00000000 @00; 0i
Debug: 276 33 riscv-013.c:414 scan(): hasel hartselhi=1023 hartsello=1023 dmactive ->
Debug: 277 34 riscv-013.c:404 scan(): 41b - 00000000 @10 -> + 00000000 @00; 0i
Debug: 278 34 riscv-013.c:404 scan(): 41b r 00000000 @10 -> + 00000000 @00; 0i
Debug: 279 35 riscv-013.c:404 scan(): 41b - 00000000 @10 -> + 00000000 @00; 0i
Please focus on your hardware design - especially make sure whether the SweRV processor core and the debug module are not held in reset and clocked properly. Also note that there is a separate reset signal for the debug module (dbg_rst_l
) that needs to be treated properly.
BTW, it seems that you use command riscv set_mem_access progbuf
in your .cfg file. This is incorrect as SweRV does not implement the debug program buffer. Please make sure you have SweRV 1.8 (latest version) and configure your memory access this way: riscv set_mem_access abstract
. However this is unrelated to the JTAG issue above.
Hope this helped. Again, this appears to be an issue with the hardware, not with OpenOCD. Please try asking at the SweRV repo, as noted above.
Regards, Jan
Thank you Jan! This is a great response. I really appreciate you. I will check my hardware design and may try the new SweRV core version
@kingstone1927 how did you fix your issue? i'm having a similar issue where it isn't able to read the control register to examine the target. Could you provide your openocd configuration file?
@kingstone1927 how did you fix your issue? i'm having a similar issue where it isn't able to read the control register to examine the target. Could you provide your openocd configuration file?
@kingstone1927, @wizkad, is the issue still relevant? I would like to close it.
I implemented SweRV_EH1 on a Zedboard fpga. I am trying to use openOCD and Jtag Arm-USB-Tiny_H to download code to the board as instructed in the README. I have checked the physical connection and make sure it be correctly connected to the Pmod on the Zedboard. Does anyone know what could potentially cause this error and ways to fix it? I would really appreciate it.
I run:
openocd -f swerv_openocd.cfg
here is the error I got:Here is what it shows when I run with -d3 flag