What does openocd use to judge the soc XLEN？

[Damien-Wu]

The arch of my soc is rv32 and misa = 40000100(indicates xlen is 32),but openocd shows XLEN=64.When i open gdb ,openocd instantly shows:"dropped 'gdb' connection".

[TommyMurphyTM1234]

What does openocd use to judge the soc XLEN？

This is how OpenOCD detects the target XLEN (I'm assuming that your target is not using a "legacy" 0.11 debug block):

• https://github.com/riscv/riscv-openocd/blob/78231cda38b6e01e87ba69d9878a9a7d56dd0c14/src/target/riscv/riscv-013.c#L1705

You probably need to provide more details - for example:

• Details of your target.
• OpenOCD verbose log using openocd -d3 ....
• Details of your OpenOCD/GDB setup including the OpenOCD script used, and GDB (e.g. .gdbinit etc.) commands executed early on automatically or manually.
• What happens if you just use the OpenOCD telnet interface to eliminate GDB from the picture temporarily.

but openocd shows XLEN=64

Where exactly?

[TommyMurphyTM1234]

Any update @Damien-Wu?

BTW - while OpenOCD dynamic detection of the XLEN should work - and it remains to be seen if/why this is not happening in your case - it should also be possible to explicitly specify the XLEN via GDB using set architecture riscv:rv32 or set architecture riscv:rv64 before target remote .... This should not be necessary since dynamic detection of the XLEN should work. But it may help you while investigating or to make progress while the issue persists for you.

• https://sourceware.org/gdb/onlinedocs/gdb/Targets.html
• https://eclipse-embed-cdt.github.io/debug/openocd/riscv/

[Damien-Wu]

@TommyMurphyTM1234 Thanks for answer. This is my openocd.cfg

interface remote_bitbang
remote_bitbang_port 44853
remote_bitbang_host localhost
if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME riscv
}
if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x00360a79
}
jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME 
$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 8192 -endian little
riscv expose_csrs 3040-3071
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_command_timeout_sec 1200
riscv set_reset_timeout_sec 10

Additionly,i used set arch riscv:rv32 before target remote,this is my gdbinit:

set architecture riscv:rv32 
target extended-remote :3333
file app/dummy/dummy.elf

When i execute It shows

warning: Selected architecture riscv:rv32 is ambiguous withreported target architecture riscv:rv64
warning: No executable has been specified and target does not support
determining executable automatically.  Try using the "file" command.

I just read the riscv-013.c and confused about the function register_read_abstract,the return value is always ERRO_OK.

[TommyMurphyTM1234]

You haven't provided the other info that I suggested earlier, in particular the verbose OpenOCD log.

[Damien-Wu]

@TommyMurphyTM1234 Sorry,this is OpenOCD log：

Open On-Chip Debugger 0.12.0+dev-01139-g99ec57609 (2023-04-04-11:45)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
User : 3 1 options.c:52 configuration_output_handler(): debug_level: 3User : 4 1 options.c:52 configuration_output_handler(): 
Debug: 5 1 configuration.c:33 add_script_search_dir(): adding ./verilator/util/openocd/
Debug: 6 2 options.c:233 add_default_dirs(): bindir=/home/ww/riscv/riscv/bin
Debug: 7 2 options.c:234 add_default_dirs(): pkgdatadir=/home/ww/riscv/riscv/share/openocd
Debug: 8 2 options.c:235 add_default_dirs(): exepath=/home/ww/riscv/riscv/bin
Debug: 9 2 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 10 2 configuration.c:33 add_script_search_dir(): adding /home/ww/.config/openocd
Debug: 11 2 configuration.c:33 add_script_search_dir(): adding /home/ww/.openocd
Debug: 12 2 configuration.c:33 add_script_search_dir(): adding /home/ww/riscv/riscv/bin/../share/openocd/site
Debug: 13 2 configuration.c:33 add_script_search_dir(): adding /home/ww/riscv/riscv/bin/../share/openocd/scripts
Debug: 14 2 command.c:152 script_debug(): command - ocd_find openocd.cfg
Debug: 15 2 configuration.c:88 find_file(): found ./verilator/util/openocd//openocd.cfg
Debug: 16 2 command.c:152 script_debug(): command - echo DEPRECATED! use 'adapter driver' not 'interface'
User : 17 2 command.c:690 handle_echo(): DEPRECATED! use 'adapter driver' not 'interface'
Debug: 18 2 command.c:152 script_debug(): command - adapter driver remote_bitbang
Info : 19 2 transport.c:107 allow_transports(): only one transport option; autoselecting 'jtag'
Debug: 20 2 command.c:152 script_debug(): command - echo DEPRECATED! use 'remote_bitbang port' not 'remote_bitbang_port'
User : 21 2 command.c:690 handle_echo(): DEPRECATED! use 'remote_bitbang port' not 'remote_bitbang_port'
Debug: 22 2 command.c:152 script_debug(): command - remote_bitbang port 44853
Debug: 23 2 command.c:152 script_debug(): command - echo DEPRECATED! use 'remote_bitbang host' not 'remote_bitbang_host'
User : 24 2 command.c:690 handle_echo(): DEPRECATED! use 'remote_bitbang host' not 'remote_bitbang_host'
Debug: 25 2 command.c:152 script_debug(): command - remote_bitbang host localhost
Debug: 26 2 command.c:152 script_debug(): command - jtag newtap riscv tap -irlen 5 -expected-id 0x00360a79
Debug: 27 2 tcl.c:561 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: tap, Dotted: riscv.tap, 4 params
Debug: 28 2 tcl.c:579 jim_newtap_cmd(): Processing option: -irlen
Debug: 29 2 tcl.c:579 jim_newtap_cmd(): Processing option: -expected-id
Debug: 30 2 core.c:1474 jtag_tap_init(): Created Tap: riscv.tap @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 31 2 command.c:152 script_debug(): command - target create riscv.tap.0 riscv -chain-position riscv.tap
Debug: 32 2 target.c:2193 target_free_all_working_areas_restore(): freeing all working areas
Debug: 33 2 riscv.c:432 riscv_create_target(): riscv_create_target()
Debug: 34 2 command.c:152 script_debug(): command - riscv.tap.0 configure -work-area-phys 0x20000000 -work-area-size 8192 -endian little
Debug: 35 2 target.c:2193 target_free_all_working_areas_restore(): freeing all working areas
Debug: 36 2 target.c:2193 target_free_all_working_areas_restore(): freeing all working areas
Debug: 37 2 command.c:152 script_debug(): command - riscv expose_csrs 3040-3071
Debug: 38 2 command.c:152 script_debug(): command - gdb_report_data_abort enable
Debug: 39 2 command.c:152 script_debug(): command - gdb_report_register_access_error enable
Debug: 40 2 command.c:152 script_debug(): command - riscv set_command_timeout_sec 1200
Debug: 41 2 command.c:152 script_debug(): command - riscv set_reset_timeout_sec 10
User : 42 2 options.c:52 configuration_output_handler(): 32User : 43 2 options.c:52 configuration_output_handler(): 
Info : 44 2 server.c:297 add_service(): Listening on port 6666 for tcl connections
Info : 45 2 server.c:297 add_service(): Listening on port 4444 for telnet connections
Debug: 46 2 command.c:152 script_debug(): command - init
Debug: 47 2 command.c:152 script_debug(): command - target init
Debug: 48 2 command.c:152 script_debug(): command - target names
Debug: 49 2 command.c:152 script_debug(): command - riscv.tap.0 cget -event gdb-flash-erase-start
Debug: 50 2 command.c:152 script_debug(): command - riscv.tap.0 configure -event gdb-flash-erase-start reset init
Debug: 51 2 command.c:152 script_debug(): command - riscv.tap.0 cget -event gdb-flash-write-end
Debug: 52 2 command.c:152 script_debug(): command - riscv.tap.0 configure -event gdb-flash-write-end reset halt
Debug: 53 2 command.c:152 script_debug(): command - riscv.tap.0 cget -event gdb-attach
Debug: 54 2 command.c:152 script_debug(): command - riscv.tap.0 configure -event gdb-attach halt 1000
Debug: 55 2 target.c:1651 handle_target_init_command(): Initializing targets...
Debug: 56 2 riscv.c:445 riscv_init_target(): riscv_init_target()
Debug: 57 2 semihosting_common.c:109 semihosting_common_init():  
Info : 58 2 remote_bitbang.c:315 remote_bitbang_init(): Initializing remote_bitbang driver
Info : 59 2 remote_bitbang.c:237 remote_bitbang_init_tcp(): Connecting to localhost:44853
Info : 60 2 remote_bitbang.c:326 remote_bitbang_init(): remote_bitbang driver initialized
Info : 61 2 adapter.c:158 adapter_init(): Note: The adapter "remote_bitbang" doesn't support configurable speed
Debug: 62 2 openocd.c:133 handle_init_command(): Debug Adapter init complete
Debug: 63 2 command.c:152 script_debug(): command - transport init
Debug: 64 2 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 65 3 core.c:830 jtag_add_reset(): SRST line released
Debug: 66 3 core.c:855 jtag_add_reset(): TRST line released
Debug: 67 3 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 68 3 command.c:152 script_debug(): command - jtag arp_init
Debug: 69 3 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 70 3 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 71 3 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 72 3 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 73 33 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.tap tap/device found: 0x00360a79 (mfg: 0x53c (Efinix Inc), part: 0x0360, ver: 0x0)
Debug: 74 33 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Debug: 75 33 core.c:1421 jtag_validate_ircapture(): riscv.tap: IR capture 0x01
Debug: 76 33 command.c:152 script_debug(): command - dap init
Debug: 77 33 arm_dap.c:97 dap_init_all(): Initializing all DAPs ...
Debug: 78 33 openocd.c:150 handle_init_command(): Examining targets...
Debug: 79 33 target.c:1837 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.tap.0
Debug: 80 33 riscv.c:1121 riscv_examine(): riscv_examine()
Debug: 81 34 riscv.c:406 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x5081
Debug: 82 34 riscv.c:1131 riscv_examine(): dtmcontrol=0x5081
Debug: 83 34 riscv.c:1133 riscv_examine():   version=0x1
Debug: 84 34 riscv-013.c:2275 init_target(): init
Debug: 85 35 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x0 -> 0x5081
Debug: 86 35 riscv-013.c:1565 examine(): dtmcontrol=0x5081
Debug: 87 35 riscv-013.c:1566 examine():   dmireset=0
Debug: 88 35 riscv-013.c:1567 examine():   idle=5
Debug: 89 35 riscv-013.c:1568 examine():   dmistat=0
Debug: 90 35 riscv-013.c:1569 examine():   abits=8
Debug: 91 35 riscv-013.c:1570 examine():   version=1
Debug: 92 35 riscv-013.c:251 get_dm(): [0] Allocating new DM
Debug: 93 37 riscv-013.c:391 scan(): 42b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 94 39 riscv-013.c:391 scan(): 42b - 00000000 @10 -> b 00000000 @00; 0i
Debug: 95 39 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Debug: 96 40 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 97 41 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00000000 @00; 1i
Debug: 98 43 riscv-013.c:391 scan(): 42b w 00000001 @10 -> + 00000000 @00; 1i
Debug: 99 43 riscv-013.c:401 scan():  dmactive -> 
Debug: 100 44 riscv-013.c:391 scan(): 42b - 00000000 @10 -> b 00000000 @00; 1i
Debug: 101 44 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=2, ac_busy_delay=0
Debug: 102 45 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 103 49 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00000000 @00; 2i
Debug: 104 51 riscv-013.c:391 scan(): 42b w 07ffffc1 @10 -> + 00000000 @00; 2i
Debug: 105 51 riscv-013.c:401 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 106 52 riscv-013.c:391 scan(): 42b - 00000000 @10 -> b 00000000 @00; 2i
Debug: 107 52 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=3, ac_busy_delay=0
Debug: 108 53 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 109 54 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00000000 @00; 3i
Debug: 110 56 riscv-013.c:391 scan(): 42b r 00000000 @10 -> + 00000000 @00; 3i
Debug: 111 57 riscv-013.c:391 scan(): 42b - 00000000 @10 -> b 00000000 @00; 3i
Debug: 112 57 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=4, ac_busy_delay=0
Debug: 113 59 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 114 60 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 04000001 @10; 4i
Debug: 115 60 riscv-013.c:401 scan():  ->  hasel dmactive
Debug: 116 62 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 04000001 @10; 4i
Debug: 117 62 riscv-013.c:401 scan():  ->  hasel dmactive
Debug: 118 63 riscv-013.c:391 scan(): 42b - 00000000 @11 -> b 00000000 @00; 4i
Debug: 119 63 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=5, ac_busy_delay=0
Debug: 120 64 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 121 66 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00400ca2 @11; 5i
Debug: 122 66 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 123 66 riscv-013.c:1615 examine(): dmstatus:  0x00400ca2
Debug: 124 66 riscv-013.c:1631 examine(): hartsellen=0
Debug: 125 67 riscv-013.c:391 scan(): 42b r 00000000 @12 -> + 00400ca2 @11; 5i
Debug: 126 67 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 127 69 riscv-013.c:391 scan(): 42b - 00000000 @12 -> b 00000000 @00; 5i
Debug: 128 69 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=6, ac_busy_delay=0
Debug: 129 70 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 130 71 riscv-013.c:391 scan(): 42b - 00000000 @12 -> + 00010000 @12; 6i
Debug: 131 73 riscv-013.c:391 scan(): 42b r 00000000 @38 -> + 00010000 @12; 6i
Debug: 132 74 riscv-013.c:391 scan(): 42b - 00000000 @38 -> b 00000000 @00; 6i
Debug: 133 74 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=7, ac_busy_delay=0
Debug: 134 76 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 135 78 riscv-013.c:391 scan(): 42b - 00000000 @38 -> + 20040044 @38; 7i
Debug: 136 78 riscv-013.c:401 scan():  ->  sbversion=1 sbaccess=2 sbasize=2 sbaccess32
Debug: 137 79 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20040044 @38; 7i
Debug: 138 79 riscv-013.c:401 scan():  ->  sbversion=1 sbaccess=2 sbasize=2 sbaccess32
Debug: 139 81 riscv-013.c:391 scan(): 42b - 00000000 @16 -> b 00000000 @00; 7i
Debug: 140 81 riscv-013.c:454 increase_dmi_busy_delay(): dtmcs_idle=5, dmi_busy_delay=8, ac_busy_delay=0
Debug: 141 82 riscv-013.c:445 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x5081
Debug: 142 84 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 143 84 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Info : 144 84 riscv-013.c:1662 examine(): datacount=1 progbufsize=15
Debug: 145 85 riscv-013.c:391 scan(): 42b r 00000000 @10 -> + 0f000001 @16; 8i
Debug: 146 85 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 147 87 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 04000001 @10; 8i
Debug: 148 87 riscv-013.c:401 scan():  ->  hasel dmactive
Debug: 149 88 riscv-013.c:391 scan(): 42b w 04000001 @10 -> + 04000001 @10; 8i
Debug: 150 88 riscv-013.c:401 scan():  hasel dmactive ->  hasel dmactive
Debug: 151 90 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 04000001 @10; 8i
Debug: 152 90 riscv-013.c:401 scan():  ->  hasel dmactive
Debug: 153 91 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 04000001 @10; 8i
Debug: 154 91 riscv-013.c:401 scan():  ->  hasel dmactive
Debug: 155 93 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00400ca2 @11; 8i
Debug: 156 93 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 157 93 riscv-013.c:1700 examine(): Detected 1 harts.
Debug: 158 94 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00400ca2 @11; 8i
Debug: 159 94 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 160 96 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00400ca2 @11; 8i
Debug: 161 96 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 162 96 riscv-013.c:4173 select_prepped_harts(): index=0, coreid=0, prepped=0
Debug: 163 96 riscv-013.c:4212 riscv013_halt_go(): halting hart 0
Debug: 164 97 riscv-013.c:391 scan(): 42b w 80000001 @10 -> + 00400ca2 @11; 8i
Debug: 165 97 riscv-013.c:401 scan(): haltreq dmactive ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 166 99 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00400ca2 @11; 8i
Debug: 167 99 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 168 100 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00400ca2 @11; 8i
Debug: 169 100 riscv-013.c:401 scan():  ->  impebreak allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 170 102 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 171 102 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 172 103 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 173 103 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 174 105 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 175 105 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 176 106 riscv-013.c:391 scan(): 42b w 00000001 @10 -> + 004003a2 @11; 8i
Debug: 177 106 riscv-013.c:401 scan():  dmactive ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 178 108 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 004003a2 @11; 8i
Debug: 179 108 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 180 108 riscv-013.c:776 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 181 109 riscv-013.c:391 scan(): 42b w 00321008 @17 -> + 004003a2 @11; 8i
Debug: 182 109 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 183 111 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 004003a2 @11; 8i
Debug: 184 111 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 185 112 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 186 112 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 187 112 riscv-013.c:776 execute_abstract_command(): command=0x320301; access register, size=64, postexec=0, transfer=1, write=0, regno=0x301
Debug: 188 114 riscv-013.c:391 scan(): 42b w 00320301 @17 -> + 0f000001 @16; 8i
Debug: 189 114 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 190 115 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 0f000001 @16; 8i
Debug: 191 115 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 192 117 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 193 117 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 194 118 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 195 118 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 196 120 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 197 121 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 198 123 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 40000100 @04; 8i
Debug: 199 123 riscv-013.c:1486 register_read_direct(): {0} misa = 0x40000100
Debug: 200 123 riscv.c:3807 riscv_init_registers(): create register cache for 4194 registers
Debug: 201 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3040 (name=csr3040)
Debug: 202 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3041 (name=csr3041)
Debug: 203 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3042 (name=csr3042)
Debug: 204 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3043 (name=csr3043)
Debug: 205 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3044 (name=csr3044)
Debug: 206 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3045 (name=csr3045)
Debug: 207 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3046 (name=csr3046)
Debug: 208 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3047 (name=csr3047)
Debug: 209 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3048 (name=csr3048)
Debug: 210 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3049 (name=csr3049)
Debug: 211 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3050 (name=csr3050)
Debug: 212 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3051 (name=csr3051)
Debug: 213 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3052 (name=csr3052)
Debug: 214 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3053 (name=csr3053)
Debug: 215 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3054 (name=csr3054)
Debug: 216 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3055 (name=csr3055)
Debug: 217 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3056 (name=csr3056)
Debug: 218 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3057 (name=csr3057)
Debug: 219 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3058 (name=csr3058)
Debug: 220 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3059 (name=csr3059)
Debug: 221 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3060 (name=csr3060)
Debug: 222 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3061 (name=csr3061)
Debug: 223 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3062 (name=csr3062)
Debug: 224 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3063 (name=csr3063)
Debug: 225 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3064 (name=csr3064)
Debug: 226 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3065 (name=csr3065)
Debug: 227 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3066 (name=csr3066)
Debug: 228 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3067 (name=csr3067)
Debug: 229 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3068 (name=csr3068)
Debug: 230 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3069 (name=csr3069)
Debug: 231 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3070 (name=csr3070)
Debug: 232 123 riscv.c:4349 riscv_init_registers(): Exposing additional CSR 3071 (name=csr3071)
Debug: 233 123 riscv-013.c:1750 examine():  hart 0: XLEN=64, misa=0x40000100
Debug: 234 123 riscv-013.c:4439 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 235 124 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 40000100 @04; 8i
Debug: 236 126 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 237 126 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 238 127 riscv-013.c:391 scan(): 42b w 40000001 @10 -> + 004003a2 @11; 8i
Debug: 239 127 riscv-013.c:401 scan():  resumereq dmactive ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 240 129 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 004003a2 @11; 8i
Debug: 241 129 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 242 131 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 243 131 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 244 132 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 245 132 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 246 134 riscv-013.c:391 scan(): 42b w 00000001 @10 -> + 00430ca2 @11; 8i
Debug: 247 134 riscv-013.c:401 scan():  dmactive ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 248 135 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00430ca2 @11; 8i
Debug: 249 135 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Info : 250 135 riscv-013.c:1773 examine(): Examined RISC-V core; found 1 harts
Info : 251 135 riscv-013.c:1775 examine():  hart 0: XLEN=64, misa=0x40000100
Debug: 252 135 target.c:1837 target_call_event_callbacks(): target event 21 (examine-end) for core riscv.tap.0
Debug: 253 135 command.c:152 script_debug(): command - flash init
Debug: 254 135 tcl.c:1363 handle_flash_init_command(): Initializing flash devices...
Debug: 255 135 command.c:152 script_debug(): command - nand init
Debug: 256 135 tcl.c:487 handle_nand_init_command(): Initializing NAND devices...
Debug: 257 135 command.c:152 script_debug(): command - pld init
Debug: 258 135 pld.c:194 handle_pld_init_command(): Initializing PLDs...
Debug: 259 135 command.c:152 script_debug(): command - tpiu init
Info : 260 135 gdb_server.c:3791 gdb_target_start(): starting gdb server for riscv.tap.0 on 3333
Info : 261 135 server.c:297 add_service(): Listening on port 3333 for gdb connections
Debug: 262 235 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 263 235 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 264 235 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=0
Debug: 265 236 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 266 236 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 267 238 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 268 238 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 269 238 riscv.c:2101 riscv_poll_hart():   triggered running
Debug: 270 335 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 271 335 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 272 335 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 273 337 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 274 337 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 275 338 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 276 338 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 277 436 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 278 436 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 279 436 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 280 437 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 281 437 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 282 439 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 283 439 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 284 536 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 285 537 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 286 537 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 287 538 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 288 538 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 289 540 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 290 540 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 291 636 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 292 636 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 293 636 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 294 638 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 295 638 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 296 639 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 297 639 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 298 737 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 299 737 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 300 737 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 301 741 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 302 741 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 303 742 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 304 742 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 305 837 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 306 837 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 307 838 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 308 839 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 309 839 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 310 840 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 311 840 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 312 938 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 313 938 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 314 938 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 315 939 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 316 939 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 317 941 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 318 941 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 319 1037 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 320 1037 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 321 1037 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 322 1039 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 323 1039 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 324 1040 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 325 1040 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 326 1137 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 327 1138 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 328 1138 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 329 1139 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 330 1139 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 331 1141 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 332 1141 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 333 1237 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 334 1237 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 335 1237 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 336 1239 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 337 1239 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 338 1240 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 339 1240 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 340 1338 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 341 1338 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 342 1338 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 343 1339 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 344 1339 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 345 1341 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 346 1341 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 347 1437 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 348 1437 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 349 1437 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 350 1439 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 351 1439 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 352 1440 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 353 1440 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 354 1537 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 355 1537 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 356 1537 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 357 1539 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 358 1539 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 359 1540 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 360 1540 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 361 1638 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 362 1638 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 363 1638 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 364 1639 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 365 1639 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 366 1641 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 367 1641 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 368 1738 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 369 1738 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 370 1738 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 371 1741 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 372 1741 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 373 1744 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 374 1744 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 375 1839 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 376 1839 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 377 1839 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 378 1840 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 379 1840 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 380 1842 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 381 1842 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 382 1939 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 383 1939 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 384 1939 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 385 1941 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 386 1941 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 387 1942 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 388 1942 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 389 2040 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 390 2040 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 391 2040 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 392 2041 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 393 2041 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 394 2043 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 395 2043 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 396 2140 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 397 2140 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 398 2140 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 399 2142 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 400 2142 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 401 2143 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 402 2143 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 403 2241 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 404 2241 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 405 2241 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 406 2242 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 407 2242 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 408 2244 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 409 2244 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 410 2341 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 411 2341 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 412 2341 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 413 2343 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 414 2343 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 415 2344 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 416 2344 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 417 2441 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 418 2441 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 419 2441 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 420 2443 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 421 2443 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 422 2444 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 423 2444 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 424 2541 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 425 2541 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 426 2541 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 427 2542 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 428 2542 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 429 2543 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 430 2543 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 431 2641 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 432 2641 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 433 2641 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=1
Debug: 434 2643 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 435 2643 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 436 2644 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 437 2644 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Info : 438 2709 server.c:90 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 439 2709 breakpoints.c:362 breakpoint_clear_target_internal(): Delete all breakpoints for target: riscv.tap.0
Debug: 440 2709 breakpoints.c:542 watchpoint_clear_target(): Delete all watchpoints for target: riscv.tap.0
Debug: 441 2709 target.c:1837 target_call_event_callbacks(): target event 22 (gdb-attach) for core riscv.tap.0
Debug: 442 2709 target.c:5061 target_handle_event(): target(0): riscv.tap.0 (riscv) event: 22 (gdb-attach) action: halt 1000
Debug: 443 2709 command.c:152 script_debug(): command - halt 1000
Debug: 444 2709 target.c:3299 handle_halt_command(): -
Debug: 445 2709 riscv.c:1235 riscv_halt(): [0] halting all harts
Debug: 446 2709 riscv.c:1170 halt_prep(): [riscv.tap.0] prep hart, debug_reason=5
Debug: 447 2709 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 448 2710 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 449 2710 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 450 2712 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 451 2712 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 452 2712 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 453 2713 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 454 2713 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 455 2714 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 456 2714 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 457 2714 riscv-013.c:4173 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 458 2714 riscv-013.c:4212 riscv013_halt_go(): halting hart 0
Debug: 459 2715 riscv-013.c:391 scan(): 42b w 80000001 @10 -> + 00430ca2 @11; 8i
Debug: 460 2716 riscv-013.c:401 scan(): haltreq dmactive ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 461 2717 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 00430ca2 @11; 8i
Debug: 462 2717 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 463 2718 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 00430ca2 @11; 8i
Debug: 464 2718 riscv-013.c:401 scan():  ->  impebreak allresumeack anyresumeack allrunning anyrunning authenticated hasresethaltreq version=2
Debug: 465 2720 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 466 2720 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 467 2729 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 468 2729 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 469 2731 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 470 2731 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 471 2732 riscv-013.c:391 scan(): 42b w 00000001 @10 -> + 004003a2 @11; 8i
Debug: 472 2732 riscv-013.c:401 scan():  dmactive ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 473 2733 riscv-013.c:391 scan(): 42b - 00000000 @10 -> + 004003a2 @11; 8i
Debug: 474 2733 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 475 2733 riscv.c:3230 riscv_invalidate_register_cache(): [0]
Debug: 476 2733 target.c:1837 target_call_event_callbacks(): target event 0 (gdb-halt) for core riscv.tap.0
Debug: 477 2733 target.c:1837 target_call_event_callbacks(): target event 1 (halted) for core riscv.tap.0
Debug: 478 2733 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 479 2733 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 480 2733 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 481 2735 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 482 2735 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 483 2736 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 484 2736 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 485 2736 gdb_server.c:1070 gdb_new_connection(): New GDB Connection: 1, Target riscv.tap.0, state: halted
Debug: 486 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+;memory-tagging+
Debug: 487 2737 riscv.c:1764 riscv_get_gdb_reg_list_internal(): [riscv.tap.0] {0} reg_class=0, read=0
Debug: 488 2737 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 489 2737 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $PacketSize=4000;qXfer:memory-map:read-;qXfer:features:read+;qXfer:threads:read+;QStartNoAckMode+;vContSupported+#04
Debug: 490 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: +
Debug: 491 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: vMustReplyEmpty
Debug: 492 2737 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $#00
Debug: 493 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: +
Debug: 494 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: QStartNoAckMode
Debug: 495 2737 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $OK#9a
Debug: 496 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: +
Debug: 497 2737 gdb_server.c:693 gdb_get_packet_inner(): Received first acknowledgment after entering noack mode. Ignoring it.
Debug: 498 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: !
Debug: 499 2737 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $OK#9a
Debug: 500 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: Hg0
Debug: 501 2737 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $OK#9a
Debug: 502 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:0,1000
Debug: 503 2737 riscv.c:1764 riscv_get_gdb_reg_list_internal(): [riscv.tap.0] {0} reg_class=0, read=0
Debug: 504 2737 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 505 2737 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#8e
Debug: 506 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:1000,1000
Debug: 507 2737 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#dd
Debug: 508 2737 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:2000,1000
Debug: 509 2737 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#40
Debug: 510 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:3000,1000
Debug: 511 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#41
Debug: 512 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:4000,1000
Debug: 513 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#7b
Debug: 514 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:5000,1000
Debug: 515 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#a3
Debug: 516 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:6000,1000
Debug: 517 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#00
Debug: 518 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:7000,1000
Debug: 519 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-4097-bytes>#55
Debug: 520 2738 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:features:read:target.xml:8000,1000
Debug: 521 2738 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-1554-bytes>#80
Debug: 522 2740 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qTStatus
Debug: 523 2740 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $#00
Debug: 524 2740 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: ?
Debug: 525 2740 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $S02#b5
Debug: 526 2741 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:threads:read::0,1000
Debug: 527 2741 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-44-bytes>#02
Debug: 528 2741 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 529 2741 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 530 2741 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 531 2742 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 532 2742 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 533 2743 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 534 2743 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 535 2743 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: Hc-1
Debug: 536 2743 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $OK#9a
Debug: 537 2743 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qC
Debug: 538 2743 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $QC0#c4
Debug: 539 2743 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qAttached
Debug: 540 2743 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $1#31
Debug: 541 2744 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: g
Debug: 542 2744 riscv.c:1764 riscv_get_gdb_reg_list_internal(): [riscv.tap.0] {0} reg_class=1, read=1
Debug: 543 2744 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 544 2744 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register zero
Debug: 545 2744 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 546 2744 riscv.c:3366 riscv_get_register(): [riscv.tap.0] zero: 0
Debug: 547 2744 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from zero (valid=1)
Debug: 548 2744 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register ra
Debug: 549 2744 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 550 2744 riscv-013.c:776 execute_abstract_command(): command=0x321001; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 551 2745 riscv-013.c:391 scan(): 42b w 00321001 @17 -> + 004003a2 @11; 8i
Debug: 552 2745 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 553 2747 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 004003a2 @11; 8i
Debug: 554 2747 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 555 2748 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 556 2748 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 557 2749 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 558 2749 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 559 2750 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 560 2752 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 561 2761 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20070e2c @04; 8i
Debug: 562 2762 riscv-013.c:1486 register_read_direct(): {0} ra = 0x20070e2c
Debug: 563 2762 riscv.c:3366 riscv_get_register(): [riscv.tap.0] ra: 20070e2c
Debug: 564 2762 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020070e2c from ra (valid=1)
Debug: 565 2762 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register sp
Debug: 566 2762 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 567 2762 riscv-013.c:776 execute_abstract_command(): command=0x321002; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 568 2764 riscv-013.c:391 scan(): 42b w 00321002 @17 -> + 20070e2c @04; 8i
Debug: 569 2765 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20070e2c @04; 8i
Debug: 570 2767 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 571 2767 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 572 2768 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 573 2768 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 574 2770 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 575 2771 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 576 2773 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20078e04 @04; 8i
Debug: 577 2773 riscv-013.c:1486 register_read_direct(): {0} sp = 0x20078e04
Debug: 578 2773 riscv.c:3366 riscv_get_register(): [riscv.tap.0] sp: 20078e04
Debug: 579 2773 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020078e04 from sp (valid=1)
Debug: 580 2773 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register gp
Debug: 581 2773 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 582 2773 riscv-013.c:776 execute_abstract_command(): command=0x321003; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 583 2774 riscv-013.c:391 scan(): 42b w 00321003 @17 -> + 20078e04 @04; 8i
Debug: 584 2776 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20078e04 @04; 8i
Debug: 585 2777 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 586 2777 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 587 2778 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 588 2778 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 589 2780 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 590 2781 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 591 2782 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20071e00 @04; 8i
Debug: 592 2782 riscv-013.c:1486 register_read_direct(): {0} gp = 0x20071e00
Debug: 593 2782 riscv.c:3366 riscv_get_register(): [riscv.tap.0] gp: 20071e00
Debug: 594 2782 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020071e00 from gp (valid=1)
Debug: 595 2782 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register tp
Debug: 596 2782 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 597 2782 riscv-013.c:776 execute_abstract_command(): command=0x321004; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 598 2784 riscv-013.c:391 scan(): 42b w 00321004 @17 -> + 20071e00 @04; 8i
Debug: 599 2786 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20071e00 @04; 8i
Debug: 600 2788 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 601 2788 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 602 2789 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 603 2789 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 604 2791 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 605 2792 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 606 2793 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 607 2793 riscv-013.c:1486 register_read_direct(): {0} tp = 0x0
Debug: 608 2793 riscv.c:3366 riscv_get_register(): [riscv.tap.0] tp: 0
Debug: 609 2793 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from tp (valid=1)
Debug: 610 2793 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t0
Debug: 611 2793 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 612 2793 riscv-013.c:776 execute_abstract_command(): command=0x321005; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 613 2795 riscv-013.c:391 scan(): 42b w 00321005 @17 -> + 00000000 @04; 8i
Debug: 614 2796 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 615 2798 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 616 2798 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 617 2799 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 618 2799 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 619 2801 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 620 2802 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 621 2803 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 622 2803 riscv-013.c:1486 register_read_direct(): {0} t0 = 0x0
Debug: 623 2803 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t0: 0
Debug: 624 2803 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t0 (valid=1)
Debug: 625 2803 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t1
Debug: 626 2803 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 627 2803 riscv-013.c:776 execute_abstract_command(): command=0x321006; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 628 2805 riscv-013.c:391 scan(): 42b w 00321006 @17 -> + 00000000 @04; 8i
Debug: 629 2806 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 630 2808 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 631 2808 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 632 2809 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 633 2809 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 634 2810 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 635 2812 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 636 2813 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 637 2813 riscv-013.c:1486 register_read_direct(): {0} t1 = 0x0
Debug: 638 2813 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t1: 0
Debug: 639 2813 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t1 (valid=1)
Debug: 640 2813 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t2
Debug: 641 2813 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 642 2813 riscv-013.c:776 execute_abstract_command(): command=0x321007; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 643 2814 riscv-013.c:391 scan(): 42b w 00321007 @17 -> + 00000000 @04; 8i
Debug: 644 2816 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 645 2817 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 646 2817 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 647 2819 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 648 2819 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 649 2820 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 650 2821 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 651 2823 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 652 2823 riscv-013.c:1486 register_read_direct(): {0} t2 = 0x0
Debug: 653 2823 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t2: 0
Debug: 654 2823 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t2 (valid=1)
Debug: 655 2823 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s0
Debug: 656 2823 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 657 2823 riscv-013.c:776 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 658 2824 riscv-013.c:391 scan(): 42b w 00321008 @17 -> + 00000000 @04; 8i
Debug: 659 2826 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 660 2827 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 661 2827 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 662 2828 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 663 2828 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 664 2830 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 665 2831 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 666 2832 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20078e14 @04; 8i
Debug: 667 2832 riscv-013.c:1486 register_read_direct(): {0} s0 = 0x20078e14
Debug: 668 2832 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s0: 20078e14
Debug: 669 2832 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020078e14 from fp (valid=1)
Debug: 670 2832 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s1
Debug: 671 2832 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 672 2832 riscv-013.c:776 execute_abstract_command(): command=0x321009; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 673 2834 riscv-013.c:391 scan(): 42b w 00321009 @17 -> + 20078e14 @04; 8i
Debug: 674 2835 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20078e14 @04; 8i
Debug: 675 2836 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 676 2836 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 677 2838 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 678 2838 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 679 2839 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 680 2840 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 681 2842 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 682 2842 riscv-013.c:1486 register_read_direct(): {0} s1 = 0x0
Debug: 683 2842 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s1: 0
Debug: 684 2842 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s1 (valid=1)
Debug: 685 2842 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a0
Debug: 686 2842 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 687 2842 riscv-013.c:776 execute_abstract_command(): command=0x32100a; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 688 2843 riscv-013.c:391 scan(): 42b w 0032100a @17 -> + 00000000 @04; 8i
Debug: 689 2845 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 690 2846 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 691 2846 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 692 2848 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 693 2848 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 694 2849 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 695 2851 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 696 2852 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20070e44 @04; 8i
Debug: 697 2852 riscv-013.c:1486 register_read_direct(): {0} a0 = 0x20070e44
Debug: 698 2852 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a0: 20070e44
Debug: 699 2852 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020070e44 from a0 (valid=1)
Debug: 700 2852 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a1
Debug: 701 2852 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 702 2852 riscv-013.c:776 execute_abstract_command(): command=0x32100b; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 703 2853 riscv-013.c:391 scan(): 42b w 0032100b @17 -> + 20070e44 @04; 8i
Debug: 704 2855 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20070e44 @04; 8i
Debug: 705 2856 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 706 2856 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 707 2858 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 708 2858 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 709 2859 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 710 2860 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 711 2861 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20070e40 @04; 8i
Debug: 712 2861 riscv-013.c:1486 register_read_direct(): {0} a1 = 0x20070e40
Debug: 713 2861 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a1: 20070e40
Debug: 714 2861 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020070e40 from a1 (valid=1)
Debug: 715 2861 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a2
Debug: 716 2861 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 717 2861 riscv-013.c:776 execute_abstract_command(): command=0x32100c; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 718 2863 riscv-013.c:391 scan(): 42b w 0032100c @17 -> + 20070e40 @04; 8i
Debug: 719 2864 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20070e40 @04; 8i
Debug: 720 2866 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 721 2866 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 722 2867 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 723 2867 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 724 2869 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 725 2870 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 726 2871 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20070e10 @04; 8i
Debug: 727 2871 riscv-013.c:1486 register_read_direct(): {0} a2 = 0x20070e10
Debug: 728 2871 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a2: 20070e10
Debug: 729 2871 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020070e10 from a2 (valid=1)
Debug: 730 2871 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a3
Debug: 731 2871 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 732 2871 riscv-013.c:776 execute_abstract_command(): command=0x32100d; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 733 2873 riscv-013.c:391 scan(): 42b w 0032100d @17 -> + 20070e10 @04; 8i
Debug: 734 2874 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20070e10 @04; 8i
Debug: 735 2875 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 736 2875 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 737 2877 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 738 2877 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 739 2878 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 740 2880 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 741 2881 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 20000000 @04; 8i
Debug: 742 2881 riscv-013.c:1486 register_read_direct(): {0} a3 = 0x20000000
Debug: 743 2881 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a3: 20000000
Debug: 744 2881 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000020000000 from a3 (valid=1)
Debug: 745 2881 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a4
Debug: 746 2881 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 747 2881 riscv-013.c:776 execute_abstract_command(): command=0x32100e; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 748 2883 riscv-013.c:391 scan(): 42b w 0032100e @17 -> + 20000000 @04; 8i
Debug: 749 2884 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 20000000 @04; 8i
Debug: 750 2886 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 751 2886 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 752 2887 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 753 2887 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 754 2888 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 755 2890 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 756 2891 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00800000 @04; 8i
Debug: 757 2891 riscv-013.c:1486 register_read_direct(): {0} a4 = 0x800000
Debug: 758 2891 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a4: 800000
Debug: 759 2891 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000800000 from a4 (valid=1)
Debug: 760 2891 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a5
Debug: 761 2891 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 762 2891 riscv-013.c:776 execute_abstract_command(): command=0x32100f; access register, size=64, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 763 2892 riscv-013.c:391 scan(): 42b w 0032100f @17 -> + 00800000 @04; 8i
Debug: 764 2894 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00800000 @04; 8i
Debug: 765 2895 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 766 2895 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 767 2897 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 768 2897 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 769 2898 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 770 2899 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 771 2901 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000001 @04; 8i
Debug: 772 2901 riscv-013.c:1486 register_read_direct(): {0} a5 = 0x1
Debug: 773 2901 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a5: 1
Debug: 774 2901 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000001 from a5 (valid=1)
Debug: 775 2901 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a6
Debug: 776 2901 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 777 2901 riscv-013.c:776 execute_abstract_command(): command=0x321010; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 778 2902 riscv-013.c:391 scan(): 42b w 00321010 @17 -> + 00000001 @04; 8i
Debug: 779 2904 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000001 @04; 8i
Debug: 780 2905 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 781 2905 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 782 2907 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 783 2907 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 784 2908 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 785 2910 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 786 2911 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 787 2911 riscv-013.c:1486 register_read_direct(): {0} a6 = 0x0
Debug: 788 2911 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a6: 0
Debug: 789 2911 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from a6 (valid=1)
Debug: 790 2911 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register a7
Debug: 791 2911 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 792 2911 riscv-013.c:776 execute_abstract_command(): command=0x321011; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 793 2912 riscv-013.c:391 scan(): 42b w 00321011 @17 -> + 00000000 @04; 8i
Debug: 794 2914 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 795 2915 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 796 2915 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 797 2916 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 798 2916 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 799 2918 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 800 2919 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 801 2920 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 802 2920 riscv-013.c:1486 register_read_direct(): {0} a7 = 0x0
Debug: 803 2920 riscv.c:3366 riscv_get_register(): [riscv.tap.0] a7: 0
Debug: 804 2920 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from a7 (valid=1)
Debug: 805 2920 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s2
Debug: 806 2920 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 807 2920 riscv-013.c:776 execute_abstract_command(): command=0x321012; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 808 2922 riscv-013.c:391 scan(): 42b w 00321012 @17 -> + 00000000 @04; 8i
Debug: 809 2923 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 810 2925 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 811 2925 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 812 2926 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 813 2926 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 814 2928 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 815 2929 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 816 2930 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 817 2930 riscv-013.c:1486 register_read_direct(): {0} s2 = 0x0
Debug: 818 2930 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s2: 0
Debug: 819 2930 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s2 (valid=1)
Debug: 820 2930 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s3
Debug: 821 2930 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 822 2930 riscv-013.c:776 execute_abstract_command(): command=0x321013; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 823 2932 riscv-013.c:391 scan(): 42b w 00321013 @17 -> + 00000000 @04; 8i
Debug: 824 2933 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 825 2934 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 826 2934 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 827 2936 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 828 2936 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 829 2937 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 830 2939 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 831 2940 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 832 2940 riscv-013.c:1486 register_read_direct(): {0} s3 = 0x0
Debug: 833 2940 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s3: 0
Debug: 834 2940 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s3 (valid=1)
Debug: 835 2940 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s4
Debug: 836 2940 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 837 2940 riscv-013.c:776 execute_abstract_command(): command=0x321014; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 838 2942 riscv-013.c:391 scan(): 42b w 00321014 @17 -> + 00000000 @04; 8i
Debug: 839 2943 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 840 2944 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 841 2944 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 842 2946 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 843 2946 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 844 2947 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 845 2949 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 846 2950 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 847 2950 riscv-013.c:1486 register_read_direct(): {0} s4 = 0x0
Debug: 848 2950 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s4: 0
Debug: 849 2950 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s4 (valid=1)
Debug: 850 2950 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s5
Debug: 851 2950 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 852 2950 riscv-013.c:776 execute_abstract_command(): command=0x321015; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 853 2952 riscv-013.c:391 scan(): 42b w 00321015 @17 -> + 00000000 @04; 8i
Debug: 854 2953 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 855 2954 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 856 2954 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 857 2956 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 858 2956 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 859 2957 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 860 2959 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 861 2960 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 862 2960 riscv-013.c:1486 register_read_direct(): {0} s5 = 0x0
Debug: 863 2960 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s5: 0
Debug: 864 2960 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s5 (valid=1)
Debug: 865 2960 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s6
Debug: 866 2960 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 867 2960 riscv-013.c:776 execute_abstract_command(): command=0x321016; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 868 2962 riscv-013.c:391 scan(): 42b w 00321016 @17 -> + 00000000 @04; 8i
Debug: 869 2963 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 870 2964 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 871 2964 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 872 2965 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 873 2965 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 874 2967 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 875 2968 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 876 2969 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 877 2969 riscv-013.c:1486 register_read_direct(): {0} s6 = 0x0
Debug: 878 2969 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s6: 0
Debug: 879 2969 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s6 (valid=1)
Debug: 880 2969 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s7
Debug: 881 2969 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 882 2969 riscv-013.c:776 execute_abstract_command(): command=0x321017; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 883 2970 riscv-013.c:391 scan(): 42b w 00321017 @17 -> + 00000000 @04; 8i
Debug: 884 2972 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 885 2973 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 886 2973 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 887 2974 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 888 2974 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 889 2975 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 890 2977 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 891 2978 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 892 2978 riscv-013.c:1486 register_read_direct(): {0} s7 = 0x0
Debug: 893 2978 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s7: 0
Debug: 894 2978 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s7 (valid=1)
Debug: 895 2978 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s8
Debug: 896 2978 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 897 2978 riscv-013.c:776 execute_abstract_command(): command=0x321018; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 898 2979 riscv-013.c:391 scan(): 42b w 00321018 @17 -> + 00000000 @04; 8i
Debug: 899 2980 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 900 2982 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 901 2982 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 902 2983 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 903 2983 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 904 2984 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 905 2985 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 906 2987 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 907 2987 riscv-013.c:1486 register_read_direct(): {0} s8 = 0x0
Debug: 908 2987 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s8: 0
Debug: 909 2987 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s8 (valid=1)
Debug: 910 2987 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s9
Debug: 911 2987 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 912 2987 riscv-013.c:776 execute_abstract_command(): command=0x321019; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 913 2989 riscv-013.c:391 scan(): 42b w 00321019 @17 -> + 00000000 @04; 8i
Debug: 914 2990 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 915 2992 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 916 2992 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 917 2994 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 918 2994 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 919 2996 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 920 3000 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 921 3004 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 922 3004 riscv-013.c:1486 register_read_direct(): {0} s9 = 0x0
Debug: 923 3004 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s9: 0
Debug: 924 3004 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s9 (valid=1)
Debug: 925 3004 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s10
Debug: 926 3004 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 927 3004 riscv-013.c:776 execute_abstract_command(): command=0x32101a; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 928 3007 riscv-013.c:391 scan(): 42b w 0032101a @17 -> + 00000000 @04; 8i
Debug: 929 3011 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 930 3014 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 931 3014 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 932 3018 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 933 3018 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 934 3019 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 935 3021 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 936 3022 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 937 3022 riscv-013.c:1486 register_read_direct(): {0} s10 = 0x0
Debug: 938 3022 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s10: 0
Debug: 939 3022 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s10 (valid=1)
Debug: 940 3022 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register s11
Debug: 941 3022 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 942 3022 riscv-013.c:776 execute_abstract_command(): command=0x32101b; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 943 3023 riscv-013.c:391 scan(): 42b w 0032101b @17 -> + 00000000 @04; 8i
Debug: 944 3024 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 945 3026 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 946 3026 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 947 3027 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 948 3027 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 949 3028 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 950 3030 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 951 3031 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 952 3031 riscv-013.c:1486 register_read_direct(): {0} s11 = 0x0
Debug: 953 3031 riscv.c:3366 riscv_get_register(): [riscv.tap.0] s11: 0
Debug: 954 3031 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from s11 (valid=1)
Debug: 955 3031 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t3
Debug: 956 3031 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 957 3031 riscv-013.c:776 execute_abstract_command(): command=0x32101c; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 958 3032 riscv-013.c:391 scan(): 42b w 0032101c @17 -> + 00000000 @04; 8i
Debug: 959 3034 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 960 3035 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 961 3035 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 962 3037 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 963 3037 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 964 3038 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 965 3039 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 966 3040 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 967 3040 riscv-013.c:1486 register_read_direct(): {0} t3 = 0x0
Debug: 968 3040 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t3: 0
Debug: 969 3040 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t3 (valid=1)
Debug: 970 3040 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t4
Debug: 971 3040 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 972 3040 riscv-013.c:776 execute_abstract_command(): command=0x32101d; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 973 3042 riscv-013.c:391 scan(): 42b w 0032101d @17 -> + 00000000 @04; 8i
Debug: 974 3043 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 975 3044 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 976 3044 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 977 3046 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 978 3046 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 979 3047 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 980 3049 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 981 3050 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 982 3050 riscv-013.c:1486 register_read_direct(): {0} t4 = 0x0
Debug: 983 3050 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t4: 0
Debug: 984 3050 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t4 (valid=1)
Debug: 985 3050 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t5
Debug: 986 3050 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 987 3050 riscv-013.c:776 execute_abstract_command(): command=0x32101e; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 988 3051 riscv-013.c:391 scan(): 42b w 0032101e @17 -> + 00000000 @04; 8i
Debug: 989 3053 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 990 3054 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 991 3054 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 992 3056 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 993 3056 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 994 3057 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 995 3058 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 996 3060 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 997 3060 riscv-013.c:1486 register_read_direct(): {0} t5 = 0x0
Debug: 998 3060 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t5: 0
Debug: 999 3060 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t5 (valid=1)
Debug: 1000 3060 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register t6
Debug: 1001 3060 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1002 3060 riscv-013.c:776 execute_abstract_command(): command=0x32101f; access register, size=64, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 1003 3061 riscv-013.c:391 scan(): 42b w 0032101f @17 -> + 00000000 @04; 8i
Debug: 1004 3063 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 1005 3064 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 1006 3064 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1007 3066 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 1008 3066 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1009 3067 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 1010 3068 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 1011 3070 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 00000000 @04; 8i
Debug: 1012 3070 riscv-013.c:1486 register_read_direct(): {0} t6 = 0x0
Debug: 1013 3070 riscv.c:3366 riscv_get_register(): [riscv.tap.0] t6: 0
Debug: 1014 3070 riscv.c:3720 register_get(): [riscv.tap.0] read 0x0000000000000000 from t6 (valid=1)
Debug: 1015 3070 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register pc
Debug: 1016 3070 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1017 3070 riscv-013.c:776 execute_abstract_command(): command=0x3207b1; access register, size=64, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 1018 3071 riscv-013.c:391 scan(): 42b w 003207b1 @17 -> + 00000000 @04; 8i
Debug: 1019 3073 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 00000000 @04; 8i
Debug: 1020 3074 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 1021 3074 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1022 3075 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 1023 3075 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1024 3076 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 1025 3078 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 1026 3079 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 2007d9f8 @04; 8i
Debug: 1027 3079 riscv-013.c:1486 register_read_direct(): {0} dpc = 0x2007d9f8
Debug: 1028 3079 riscv-013.c:4078 riscv013_get_register(): [0] read PC from DPC: 0x2007d9f8
Debug: 1029 3079 riscv.c:3366 riscv_get_register(): [riscv.tap.0] pc: 2007d9f8
Debug: 1030 3079 riscv.c:3720 register_get(): [riscv.tap.0] read 0x000000002007d9f8 from pc (valid=0)
Debug: 1031 3079 riscv-013.c:4068 riscv013_get_register(): [riscv.tap.0] reading register pc
Debug: 1032 3079 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1033 3079 riscv-013.c:776 execute_abstract_command(): command=0x3207b1; access register, size=64, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 1034 3081 riscv-013.c:391 scan(): 42b w 003207b1 @17 -> + 2007d9f8 @04; 8i
Debug: 1035 3082 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 2007d9f8 @04; 8i
Debug: 1036 3084 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 1037 3084 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1038 3085 riscv-013.c:391 scan(): 42b r 00000000 @05 -> + 0f000001 @16; 8i
Debug: 1039 3085 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1
Debug: 1040 3086 riscv-013.c:391 scan(): 42b - 00000000 @05 -> + 00000000 @05; 8i
Debug: 1041 3088 riscv-013.c:391 scan(): 42b r 00000000 @04 -> + 00000000 @05; 8i
Debug: 1042 3089 riscv-013.c:391 scan(): 42b - 00000000 @04 -> + 2007d9f8 @04; 8i
Debug: 1043 3089 riscv-013.c:1486 register_read_direct(): {0} dpc = 0x2007d9f8
Debug: 1044 3089 riscv-013.c:4078 riscv013_get_register(): [0] read PC from DPC: 0x2007d9f8
Debug: 1045 3089 riscv.c:3366 riscv_get_register(): [riscv.tap.0] pc: 2007d9f8
Debug: 1046 3089 riscv.c:3720 register_get(): [riscv.tap.0] read 0x000000002007d9f8 from pc (valid=0)
Debug: 1047 3089 gdb_server.c:406 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $00000000000000002c0e072000000000048e072000000000001e0720000000000000000000000000000000000000000000000000000000000000000000000000148e0720000000000000000000000000440e072000000000400e072000000000100e0720000000000000002000000000000080000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8d9072000000000#9d
Debug: 1048 3089 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1049 3089 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1050 3089 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1051 3091 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 2007d9f8 @04; 8i
Debug: 1052 3092 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1053 3092 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1054 3092 gdb_server.c:390 gdb_log_incoming_packet(): [riscv.tap.0] received packet: qXfer:threads:read::0,1000
Debug: 1055 3092 gdb_server.c:403 gdb_log_outgoing_packet(): [riscv.tap.0] sending packet: $<binary-data-44-bytes>#02
Debug: 1056 3189 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1057 3189 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1058 3189 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1059 3191 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1060 3191 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1061 3192 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1062 3192 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1063 3289 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1064 3289 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1065 3289 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1066 3291 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1067 3291 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1068 3292 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1069 3292 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1070 3389 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1071 3389 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1072 3389 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1073 3390 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1074 3390 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1075 3392 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1076 3392 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1077 3489 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1078 3489 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1079 3489 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1080 3490 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1081 3490 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1082 3491 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1083 3491 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1084 3589 riscv.c:2186 riscv_openocd_poll(): polling all harts
Debug: 1085 3589 riscv.c:3220 riscv_set_current_hartid(): setting hartid to 0, was 0
Debug: 1086 3589 riscv.c:2091 riscv_poll_hart(): polling hart 0, target->state=2
Debug: 1087 3591 riscv-013.c:391 scan(): 42b r 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1088 3591 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1089 3592 riscv-013.c:391 scan(): 42b - 00000000 @11 -> + 004003a2 @11; 8i
Debug: 1090 3592 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 1364 7582 server.c:607 sig_handler(): Terminating on Signal 2
Debug: 1365 7582 command.c:152 script_debug(): command - shutdown
User : 1366 7582 server.c:758 handle_shutdown_command(): shutdown command invoked
Debug: 1367 7582 gdb_server.c:1112 gdb_connection_closed(): GDB Close, Target: riscv.tap.0, state: halted, gdb_actual_connections=0
Debug: 1368 7582 target.c:1837 target_call_event_callbacks(): target event 8 (gdb-end) for core riscv.tap.0
Debug: 1369 7582 target.c:1837 target_call_event_callbacks(): target event 23 (gdb-detach) for core riscv.tap.0
Debug: 1370 7582 riscv.c:491 riscv_deinit_target(): riscv_deinit_target()
Debug: 1371 7582 riscv-013.c:1520 deinit_target(): riscv_deinit_target()
Debug: 1372 7582 target.c:2193 target_free_all_working_areas_restore(): freeing all working areas
Info : 1373 7582 remote_bitbang.c:164 remote_bitbang_quit(): remote_bitbang interface quit

[TommyMurphyTM1234]

Debug: 233 123 riscv-013.c:1750 examine():  hart 0: XLEN=64, misa=0x40000100

This means that the 64-bit read of register s0 in examine() succeeds so OpenOCD detects the target's XLEN as 64.

• https://github.com/riscv/riscv-openocd/blob/21d2787d64952c7d794591ccda40edd21cab9cf1/src/target/riscv/riscv-013.c#L1697

You need to figure out why this is the case.

You also still haven't clarified the nature and provenance of your RISC-V target which might shed some light on what's going on/wrong.

This message must be coming from GDB because the target is detected as XLEN = 64 but the set architecture riscv:rv32 command conflicts with this.

warning: Selected architecture riscv:rv32 is ambiguous with reported target architecture riscv:rv64

[TommyMurphyTM1234]

At a glance, this seems to be the read of register s0 for the purposes of XLEN detection:

Debug: 180 108 riscv-013.c:776 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 181 109 riscv-013.c:391 scan(): 42b w 00321008 @17 -> + 004003a2 @11; 8i
Debug: 182 109 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 183 111 riscv-013.c:391 scan(): 42b r 00000000 @16 -> + 004003a2 @11; 8i
Debug: 184 111 riscv-013.c:401 scan():  ->  impebreak allhalted anyhalted authenticated hasresethaltreq version=2
Debug: 185 112 riscv-013.c:391 scan(): 42b - 00000000 @16 -> + 0f000001 @16; 8i
Debug: 186 112 riscv-013.c:401 scan():  ->  progbufsize=15 datacount=1

[TommyMurphyTM1234]

Ok, I presume that this

Info : 73 33 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.tap tap/device found: 0x00360a79 (mfg: 0x53c (Efinix Inc), part: 0x0360, ver: 0x0)

means that you're using an Efinix RISC-V (based on/derived from VexRiscv) target?

That being the case, you might want to ask Efinix about this odd XLEN detection behaviour especially because there seem to be several other OpenOCD forks associated with Efinix/VexRiscv so maybe you're expected to use one of those and not this riscv-openocd fork?

[Damien-Wu]

My target is designed for learning by myself,and the JTAG id just conflicts with Efinix.And I found the mistake！The cmderr doesn`t maintain .

[TommyMurphyTM1234]

Yes, but where did your RISC-V implementation come from? Did you take write it from scratch yourself? Is it based on some other existing IP? If so, what?

As I said, you need to figure out why a 64-bit read of register s0 is succeeding if your target RISC-V has XLEN=32. If the XLEN actually is 32 then that read should fail and OpenOCD should detect that the target XLEN is 32.

[TommyMurphyTM1234]

And I found the mistake！The cmderr doesn`t maintain .

What does that mean? If the issue is with your target and not OpenOCD then could you close this issue as invalid, please?

[Damien-Wu]

Yes,we took write it from scratch, just implemented RV32I，i wrote the core and DM module is written by another one.Through analyzing the wave ,the reason of a 64-bit read of register s0 is succeeding is the cmderr field of dmstatuscs didnt keep enough time.We didnt use any existing IP, and the implementation of Debug Mode might have some bugs .I`m just trying to debug.

f the issue is with your target and not OpenOCD then could you close this issue as invalid, please?

Thanks . I will close the issue.