Debug Module did not become active. dmcontrol=0x0

[wizkad]

Hello, i am trying to program a zedboard using openocd to a ibex core. The output error is this one:

./util/load_demo_system2.sh halt ./sw/c/build/demo/hello_world/demo
Open On-Chip Debugger 0.12.0+dev-03370-g6f028846a (2023-11-10-09:21)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
User : 3 3 options.c:52 configuration_output_handler(): debug_level: 3User : 4 3 options.c:52 configuration_output_handler(): 
Debug: 5 3 options.c:233 add_default_dirs(): bindir=/usr/local/bin
Debug: 6 3 options.c:234 add_default_dirs(): pkgdatadir=/usr/local/share/openocd
Debug: 7 3 options.c:235 add_default_dirs(): exepath=/usr/local/bin
Debug: 8 3 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 9 3 configuration.c:33 add_script_search_dir(): adding /home/jorgelarman/.config/openocd
Debug: 10 3 configuration.c:33 add_script_search_dir(): adding /home/jorgelarman/.openocd
Debug: 11 3 configuration.c:33 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site
Debug: 12 3 configuration.c:33 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts
Debug: 13 3 command.c:152 script_debug(): command - ocd_find /home/jorgelarman/work/ibex-demo-system-zedboard/util/zedboard-openocd-cfg.tcl
Debug: 14 3 configuration.c:88 find_file(): found /home/jorgelarman/work/ibex-demo-system-zedboard/util/zedboard-openocd-cfg.tcl
Debug: 15 4 command.c:152 script_debug(): command - adapter driver ftdi
Debug: 16 4 command.c:152 script_debug(): command - transport select jtag
Debug: 17 4 command.c:152 script_debug(): command - ftdi channel 0
Debug: 18 4 command.c:152 script_debug(): command - ftdi device_desc Digilent USB Device
Debug: 19 4 command.c:152 script_debug(): command - ftdi vid_pid 0x0403 0x6014
Debug: 20 4 command.c:152 script_debug(): command - ftdi layout_init 0x2088 0x3f8b
Debug: 21 4 command.c:152 script_debug(): command - reset_config srst_only srst_push_pull
Debug: 22 4 command.c:152 script_debug(): command - ftdi tdo_sample_edge falling
Debug: 23 4 command.c:152 script_debug(): command - ftdi layout_init 0x2088 0x3f8b
Debug: 24 4 command.c:152 script_debug(): command - ftdi layout_signal nSRST -data 0x2000
Debug: 25 4 command.c:152 script_debug(): command - ftdi layout_signal GPIO2 -data 0x2000
Debug: 26 4 command.c:152 script_debug(): command - ftdi layout_signal GPIO1 -data 0x0200
Debug: 27 4 command.c:152 script_debug(): command - ftdi layout_signal GPIO0 -data 0x0100
Debug: 28 4 command.c:152 script_debug(): command - jtag newtap riscv cpu -irlen 6 -expected-id 0x03727093
Debug: 29 4 tcl.c:418 handle_jtag_newtap_args(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 4 params
Debug: 30 4 core.c:1474 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 0, irlen 6, capture: 0x1 mask: 0x3
Debug: 31 4 command.c:152 script_debug(): command - jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477
Debug: 32 4 tcl.c:418 handle_jtag_newtap_args(): Creating New Tap, Chip: arm_unused, Tap: tap, Dotted: arm_unused.tap, 4 params
Debug: 33 4 core.c:1474 jtag_tap_init(): Created Tap: arm_unused.tap @ abs position 1, irlen 4, capture: 0x1 mask: 0x3
Debug: 34 4 command.c:152 script_debug(): command - target create riscv.cpu riscv -chain-position riscv.cpu
Debug: 35 4 target.c:2171 target_free_all_working_areas_restore(): freeing all working areas
Debug: 36 4 riscv.c:429 riscv_create_target(): [riscv.cpu] riscv_create_target()
Debug: 37 4 command.c:152 script_debug(): command - riscv set_ir idcode 0x09
Debug: 38 4 command.c:152 script_debug(): command - riscv set_ir dtmcs 0x22
Debug: 39 4 command.c:152 script_debug(): command - riscv set_ir dmi 0x23
Debug: 40 4 command.c:152 script_debug(): command - adapter speed 100
Debug: 41 4 adapter.c:249 adapter_config_khz(): handle adapter khz
Debug: 42 4 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 43 4 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 44 4 command.c:152 script_debug(): command - gdb_report_data_abort enable
Debug: 45 4 command.c:152 script_debug(): command - gdb_report_register_access_error enable
Debug: 46 4 command.c:152 script_debug(): command - gdb_breakpoint_override hard
User : 47 4 gdb_server.c:4041 handle_gdb_breakpoint_override_command(): force hard breakpoints
Debug: 48 4 command.c:152 script_debug(): command - reset_config none
Debug: 49 4 command.c:152 script_debug(): command - init
Debug: 50 4 command.c:152 script_debug(): command - target init
Debug: 51 4 command.c:152 script_debug(): command - target names
Debug: 52 4 command.c:152 script_debug(): command - riscv.cpu cget -event gdb-flash-erase-start
Debug: 53 4 command.c:152 script_debug(): command - riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 54 4 command.c:152 script_debug(): command - riscv.cpu cget -event gdb-flash-write-end
Debug: 55 4 command.c:152 script_debug(): command - riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 56 4 command.c:152 script_debug(): command - riscv.cpu cget -event gdb-attach
Debug: 57 4 command.c:152 script_debug(): command - riscv.cpu configure -event gdb-attach halt 1000
Debug: 58 4 target.c:1629 handle_target_init_command(): Initializing targets...
Debug: 59 4 riscv.c:442 riscv_init_target(): [riscv.cpu] riscv_init_target()
Debug: 60 4 semihosting_common.c:107 semihosting_common_init():  
Debug: 61 4 ftdi.c:732 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 62 10 mpsse.c:406 mpsse_purge(): -
Debug: 63 10 mpsse.c:687 mpsse_loopback_config(): off
Debug: 64 10 mpsse.c:732 mpsse_set_frequency(): target 100000 Hz
Debug: 65 10 mpsse.c:724 mpsse_rtck_config(): off
Debug: 66 10 mpsse.c:713 mpsse_divide_by_5_config(): off
Debug: 67 10 mpsse.c:693 mpsse_set_divisor(): 299
Debug: 68 10 mpsse.c:756 mpsse_set_frequency(): actually 100000 Hz
Debug: 69 10 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 70 10 adapter.c:217 adapter_khz_to_speed(): have adapter set up
Debug: 71 10 mpsse.c:732 mpsse_set_frequency(): target 100000 Hz
Debug: 72 10 mpsse.c:724 mpsse_rtck_config(): off
Debug: 73 10 mpsse.c:713 mpsse_divide_by_5_config(): off
Debug: 74 10 mpsse.c:693 mpsse_set_divisor(): 299
Debug: 75 10 mpsse.c:756 mpsse_set_frequency(): actually 100000 Hz
Debug: 76 10 adapter.c:213 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 77 10 adapter.c:217 adapter_khz_to_speed(): have adapter set up
Info : 78 10 adapter.c:177 adapter_init(): clock speed 100 kHz
Debug: 79 10 openocd.c:133 handle_init_command(): Debug Adapter init complete
Debug: 80 10 command.c:152 script_debug(): command - transport init
Debug: 81 10 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 82 10 core.c:830 jtag_add_reset(): SRST line released
Debug: 83 10 core.c:855 jtag_add_reset(): TRST line released
Debug: 84 10 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 85 10 command.c:152 script_debug(): command - jtag arp_init
Debug: 86 10 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 87 10 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 88 10 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 89 10 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 90 17 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Info : 91 17 core.c:1133 jtag_examine_chain_display(): JTAG tap: arm_unused.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Debug: 92 17 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Debug: 93 17 core.c:1421 jtag_validate_ircapture(): riscv.cpu: IR capture 0x35
Debug: 94 17 core.c:1421 jtag_validate_ircapture(): arm_unused.tap: IR capture 0x01
Debug: 95 17 command.c:152 script_debug(): command - dap init
Debug: 96 17 arm_dap.c:95 dap_init_all(): Initializing all DAPs ...
Debug: 97 17 openocd.c:150 handle_init_command(): Examining targets...
Debug: 98 17 target.c:1815 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 99 17 riscv.c:1590 riscv_examine(): [riscv.cpu] Starting examination
Debug: 100 18 riscv.c:398 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 101 18 riscv.c:1604 riscv_examine(): [riscv.cpu] dtmcontrol=0x1071
Debug: 102 18 riscv.c:1606 riscv_examine(): [riscv.cpu] version=0x1
Debug: 103 18 riscv-013.c:2718 init_target(): [riscv.cpu] Init.
Debug: 104 18 riscv-013.c:1853 examine(): [riscv.cpu] dbgbase=0x0
Debug: 105 19 riscv-013.c:447 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 106 19 riscv-013.c:1861 examine(): [riscv.cpu] dtmcontrol=0x1071
Debug: 107 19 riscv-013.c:1862 examine(): [riscv.cpu]   dmireset=0
Debug: 108 19 riscv-013.c:1863 examine(): [riscv.cpu]   idle=1
Debug: 109 19 riscv-013.c:1864 examine(): [riscv.cpu]   dmistat=0
Debug: 110 19 riscv-013.c:1865 examine(): [riscv.cpu]   abits=7
Debug: 111 19 riscv-013.c:1866 examine(): [riscv.cpu]   version=1
Debug: 112 19 riscv-013.c:750 check_dbgbase_exists(): [riscv.cpu] Searching for DM with DMI base address (dbgbase) = 0x0
Debug: 113 19 riscv-013.c:256 get_dm(): [riscv.cpu] Coreid [0] Allocating new DM
Debug: 114 19 riscv-013.c:489 dmi_scan(): [riscv.cpu] reset_delays_wait done
Debug: 115 20 riscv-013.c:393 scan(): 41b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 116 20 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> 
Debug: 117 21 riscv-013.c:393 scan(): 41b - 00000000 @10 -> + 00000000 @10; 0i
Debug: 118 21 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 119 22 riscv-013.c:393 scan(): 41b w 00000001 @10 -> + 00000000 @10; 0i
Debug: 120 22 riscv-013.c:403 scan(): dmcontrol=1 { dmactive=active, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 121 23 riscv-013.c:393 scan(): 41b - 00000000 @10 -> + 00000001 @10; 0i
Debug: 122 23 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=1 { dmactive=active, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 123 23 riscv-013.c:4962 riscv013_invalidate_cached_debug_buffer(): [riscv.cpu] Invalidating progbuf cache
Debug: 124 24 riscv-013.c:393 scan(): 41b w 07ffffc1 @10 -> + 00000000 @10; 0i
Debug: 125 24 riscv-013.c:403 scan(): dmcontrol=0x7ffffc1 { dmactive=active, ndmreset=0, hartsello=0x3ff, clrresethaltreq=0, hasel=multiple, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0x3ff, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 126 25 riscv-013.c:393 scan(): 41b - 00000000 @10 -> + 07ffffc1 @10; 0i
Debug: 127 25 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0x7ffffc1 { dmactive=active, ndmreset=0, hartsello=0x3ff, clrresethaltreq=0, hasel=multiple, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0x3ff, }
Debug: 128 26 riscv-013.c:393 scan(): 41b r 00000000 @10 -> + 00000000 @10; 0i
Debug: 129 26 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 130 27 riscv-013.c:393 scan(): 41b - 00000000 @10 -> + 00000000 @10; 0i
Debug: 131 27 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 132 29 riscv-013.c:393 scan(): 41b w 00000001 @10 -> + 00000000 @10; 0i
Debug: 133 29 riscv-013.c:403 scan(): dmcontrol=1 { dmactive=active, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Debug: 134 29 riscv-013.c:393 scan(): 41b - 00000000 @10 -> + 00000001 @10; 0i
Debug: 135 29 riscv-013.c:403 scan(): dmcontrol=0 { dmactive=inactive, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, } -> dmcontrol=1 { dmactive=active, ndmreset=0, hartsello=0, clrresethaltreq=0, hasel=single, ackunavail=nop, ackhavereset=nop, hartreset=0, setresethaltreq=0, resumereq=0, haltreq=0, clrkeepalive=0, setkeepalive=0, hartselhi=0, }
Error: 136 29 riscv-013.c:1911 examine(): [riscv.cpu] Debug Module did not become active. dmcontrol=0x0
Debug: 137 29 target.c:1815 target_call_event_callbacks(): target event 20 (examine-fail) for core riscv.cpu
Warn : 138 29 target.c:774 target_examine(): target riscv.cpu examination failed
Debug: 139 29 openocd.c:152 handle_init_command(): target examination failed
Debug: 140 29 command.c:152 script_debug(): command - flash init
Debug: 141 29 tcl.c:1364 handle_flash_init_command(): Initializing flash devices...
Debug: 142 29 command.c:152 script_debug(): command - nand init
Debug: 143 29 tcl.c:484 handle_nand_init_command(): Initializing NAND devices...
Debug: 144 29 command.c:152 script_debug(): command - pld init
Debug: 145 29 pld.c:250 handle_pld_init_command(): Initializing PLDs...
Debug: 146 29 command.c:152 script_debug(): command - tpiu init
Info : 147 29 gdb_server.c:3870 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 148 29 server.c:297 add_service(): Listening on port 3333 for gdb connections
Debug: 149 29 command.c:152 script_debug(): command - halt
Debug: 150 29 target.c:3268 handle_halt_command(): -
Error: 151 29 target.c:553 target_halt(): Target not examined yet
Debug: 152 29 command.c:541 run_command(): Command 'halt' failed with error code -4
User : 153 30 command.c:613 command_run_line(): 
Debug: 154 30 riscv.c:508 riscv_deinit_target(): [riscv.cpu] riscv_deinit_target()
Error: 155 30 riscv.c:421 get_target_type(): [riscv.cpu] Unsupported DTM version: -1
Error: 156 30 riscv.c:513 riscv_deinit_target(): [riscv.cpu] Could not identify target type.
Debug: 157 30 target.c:2171 target_free_all_working_areas_restore(): freeing all working areas

The configuration of openocd is in the next sectio:

# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

adapter driver ftdi
transport select jtag
ftdi channel 0

ftdi device_desc "Digilent USB Device"
ftdi vid_pid 0x0403 0x6014
ftdi layout_init 0x2088 0x3f8b
reset_config srst_only srst_push_pull
ftdi tdo_sample_edge falling
ftdi layout_init 0x2088 0x3f8b
ftdi layout_signal nSRST -data 0x2000
ftdi layout_signal GPIO2 -data 0x2000
ftdi layout_signal GPIO1 -data 0x0200
ftdi layout_signal GPIO0 -data 0x0100

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Configure JTAG expected ID
# Zedboard
set _EXPECTED_ID 0x03727093

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME 

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

adapter speed 100

gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard
reset_config none

init
halt

I created some udev rules like this:

SUBSYSTEM=="usb", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", MODE="0666"

I don't know what i'm doing wrong yesterday i managed to load a program to the core and now it doesn't work. any help or suggestion on a solution or some guidelines in order to understand what i'm doing would be helpfull.

[TommyMurphyTM1234]

Why do you think that this is an OpenOCD problem as opposed to, say, an issue with the implementation of the soft IP RISC-V core on FPGA (e.g. clocks, resets, timing issues etc.)?

Perhaps the comments here might help even if they refer to a different soft IP RISC-V core albeit what seems like the same error?

• https://github.com/riscv/riscv-openocd/issues/552

[wizkad]

One day i managed to load a program to my implementation and i didn't change the debug unit so i think the error is either in how i configure openocd or in how i create the udev rules but i'm lost and don't know how to solve this issue.

[TommyMurphyTM1234]

One day i managed to load a program to my implementation and i didn't change the debug unit so i think the error is either in how i configure openocd

What do you mean by "how I configure OpenOCD"? You mean when building it? Or do you mean the script used at runtime? Regarding the latter you should probably check with the lowRISC project/community on what sort of OpenOCD script to use. And also how to investigate FPGA integration/implementation issues today might cause debug interface problems/instability.

or in how i create the udev rules

Udev rules are almost certainly not an issue here and can be discounted if you test by running as root on which case the udev rules are irrelevant. (Running as root/sudo is not recommended generally but I'm just suggesting it here to eliminate udev rules as suspects).

[wizkad]

Thanks for the quick reply @TommyMurphyTM1234 .

What do you mean by "how I configure OpenOCD"? You mean when building it? Or do you mean the script used at runtime? Regarding the latter you should probably check with the lowRISC project/community on what sort of OpenOCD script to use. And also how to investigate FPGA integration/implementation issues today might cause debug interface problems/instability.

I'm talking about the script to launch openocd which defines the jtag chain and target. The thing is i'm using an implementation of ibex which is prepared for the arty a7 board and trying to implement it onto a zedboard. I managed to create the bitstream properly but when launching the script to launch openocd and program the core via jtag i have the above issue.

[TommyMurphyTM1234]

Ok. As I said before, especially with soft IP implemented in FPGA, there are so many issues that could be involved in a system not behaving correctly. E.g. ones that I mentioned above such as timing issues, clocks/resets etc. You probably need to get your system working in simulation first. This is way outside the scope of this repo/forum.

[newfrogg]

Hi @wizkad, have you fixed that issue. I am porting ibex to pynqz2 and get the same problem as you. The dmcontrol=0x00 and debug module is not active. Some thing like below, openocd version is 0.11.0 . If you fixed that issue, It would like to know your solution. Thank you. In Addition, I port this design on arty z7 and everything is OK, but when move to pynq. These are both zynq7000. So I believe this should be openocd issues, not issue performing soft IP in FPGA as @TommyMurphyTM1234 metioned.

User : 13 2 options.c:63 configuration_output_handler(): debug_level: 3
User : 14 2 options.c:63 configuration_output_handler(): 
Debug: 15 2 options.c:244 add_default_dirs(): bindir=/usr/bin
Debug: 16 3 options.c:245 add_default_dirs(): pkgdatadir=/usr/share/openocd
Debug: 17 3 options.c:246 add_default_dirs(): exepath=/usr/bin
Debug: 18 3 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 19 3 configuration.c:42 add_script_search_dir(): adding /home/newfrogg/.config/openocd
Debug: 20 3 configuration.c:42 add_script_search_dir(): adding /home/newfrogg/.openocd
Debug: 21 3 configuration.c:42 add_script_search_dir(): adding /usr/bin/../share/openocd/site
Debug: 22 3 configuration.c:42 add_script_search_dir(): adding /usr/bin/../share/openocd/scripts
Debug: 23 3 configuration.c:97 find_file(): found util/pynq-z2-openocd-cfg.tcl
Debug: 24 3 command.c:146 script_debug(): command - adapter driver ftdi
Debug: 26 3 command.c:146 script_debug(): command - transport select jtag
Debug: 27 3 command.c:146 script_debug(): command - ftdi_tdo_sample_edge falling
Debug: 29 3 command.c:146 script_debug(): command - ftdi_device_desc TUL
Debug: 31 3 command.c:146 script_debug(): command - ftdi_vid_pid 0x0403 0x6010
Debug: 33 3 command.c:146 script_debug(): command - ftdi_channel 0
Debug: 35 3 command.c:146 script_debug(): command - ftdi_layout_init 0x0088 0x008b
Debug: 37 3 command.c:146 script_debug(): command - reset_config none
Debug: 39 3 command.c:146 script_debug(): command - jtag newtap riscv cpu -irlen 6 -expected-id 0x23727093 -ignore-version
Debug: 40 3 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 5 params
Debug: 41 3 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 42 3 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 43 3 tcl.c:596 jim_newtap_cmd(): Processing option: -ignore-version
Debug: 44 3 core.c:1484 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 0, irlen 6, capture: 0x1 mask: 0x3
Debug: 45 3 command.c:146 script_debug(): command - jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477
Debug: 46 3 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: arm_unused, Tap: tap, Dotted: arm_unused.tap, 4 params
Debug: 47 3 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 48 3 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 49 3 core.c:1484 jtag_tap_init(): Created Tap: arm_unused.tap @ abs position 1, irlen 4, capture: 0x1 mask: 0x3
Debug: 50 3 command.c:146 script_debug(): command - target create riscv.cpu riscv -chain-position riscv.cpu
Debug: 51 3 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 52 3 command.c:146 script_debug(): command - riscv set_ir idcode 0x09
Debug: 54 3 command.c:146 script_debug(): command - riscv set_ir dtmcs 0x22
Debug: 56 3 command.c:146 script_debug(): command - riscv set_ir dmi 0x23
Debug: 58 4 command.c:146 script_debug(): command - adapter speed 1000
Debug: 60 4 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 61 4 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 62 4 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 63 4 command.c:146 script_debug(): command - riscv set_prefer_sba on
Debug: 65 4 command.c:146 script_debug(): command - gdb_report_data_abort enable
Debug: 67 4 command.c:146 script_debug(): command - gdb_report_register_access_error enable
Debug: 69 4 command.c:146 script_debug(): command - gdb_breakpoint_override hard
User : 71 4 gdb_server.c:3679 handle_gdb_breakpoint_override_command(): force hard breakpoints
Debug: 72 4 command.c:146 script_debug(): command - reset_config none
Debug: 74 4 command.c:146 script_debug(): command - init
Debug: 76 4 command.c:146 script_debug(): command - target init
Debug: 78 4 command.c:146 script_debug(): command - target names
Debug: 79 4 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-flash-erase-start
Debug: 80 4 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 81 4 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-flash-write-end
Debug: 82 4 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 83 4 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-attach
Debug: 84 4 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-attach halt 1000
Debug: 85 4 target.c:1639 handle_target_init_command(): Initializing targets...
Debug: 86 4 riscv.c:427 riscv_init_target(): riscv_init_target()
Debug: 87 4 semihosting_common.c:99 semihosting_common_init():  
Debug: 88 4 ftdi.c:650 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 89 14 mpsse.c:422 mpsse_purge(): -
Debug: 90 14 mpsse.c:703 mpsse_loopback_config(): off
Debug: 91 14 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 92 14 mpsse.c:740 mpsse_rtck_config(): off
Debug: 93 14 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 94 14 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 95 14 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 96 14 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 97 14 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 98 14 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 99 14 mpsse.c:740 mpsse_rtck_config(): off
Debug: 100 14 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 101 14 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 102 14 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 103 14 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 104 14 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 105 14 core.c:1565 adapter_init(): clock speed 1000 kHz
Debug: 106 14 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 107 14 command.c:146 script_debug(): command - transport init
Debug: 109 14 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 110 14 core.c:830 jtag_add_reset(): SRST line released
Debug: 111 14 core.c:855 jtag_add_reset(): TRST line released
Debug: 112 14 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 113 14 command.c:146 script_debug(): command - jtag arp_init
Debug: 114 14 core.c:1578 jtag_init_inner(): Init JTAG chain
Debug: 115 14 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 116 14 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 117 14 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 118 15 core.c:1142 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x23727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x2)
Info : 119 15 core.c:1142 jtag_examine_chain_display(): JTAG tap: arm_unused.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Debug: 120 15 core.c:1374 jtag_validate_ircapture(): IR capture validation scan
Debug: 121 15 core.c:1431 jtag_validate_ircapture(): riscv.cpu: IR capture 0x35
Debug: 122 15 core.c:1431 jtag_validate_ircapture(): arm_unused.tap: IR capture 0x01
Debug: 123 15 command.c:146 script_debug(): command - dap init
Debug: 125 15 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
Debug: 126 15 openocd.c:160 handle_init_command(): Examining targets...
Debug: 127 15 target.c:1825 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 128 15 riscv.c:965 riscv_examine(): riscv_examine()
Debug: 129 15 riscv.c:399 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 130 15 riscv.c:975 riscv_examine(): dtmcontrol=0x1071
Debug: 131 15 riscv.c:977 riscv_examine():   version=0x1
Debug: 132 15 riscv-013.c:2013 init_target(): init
Debug: 133 15 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 134 16 riscv-013.c:1572 examine(): dtmcontrol=0x1071
Debug: 135 16 riscv-013.c:1573 examine():   dmireset=0
Debug: 136 16 riscv-013.c:1574 examine():   idle=1
Debug: 137 16 riscv-013.c:1575 examine():   dmistat=0
Debug: 138 16 riscv-013.c:1576 examine():   abits=7
Debug: 139 16 riscv-013.c:1577 examine():   version=1
Debug: 140 16 riscv-013.c:259 get_dm(): [0] Allocating new DM
Debug: 141 16 riscv-013.c:399 scan(): 41b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 142 16 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 0i
Debug: 143 16 riscv-013.c:399 scan(): 41b w 00000001 @10 -> b 00000000 @10; 0i
Debug: 144 16 riscv-013.c:409 scan():  dmactive -> 
Debug: 145 16 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 146 16 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 147 16 riscv-013.c:399 scan(): 41b w 00000001 @10 -> + 00000000 @10; 1i
Debug: 148 16 riscv-013.c:409 scan():  dmactive -> 
Debug: 149 16 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 1i
Debug: 150 16 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 151 16 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 152 16 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 2i
Debug: 153 17 riscv-013.c:399 scan(): 41b w 07ffffc1 @10 -> b 00000000 @10; 2i
Debug: 154 17 riscv-013.c:409 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 155 17 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 156 17 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 157 17 riscv-013.c:399 scan(): 41b w 07ffffc1 @10 -> + 00000000 @10; 3i
Debug: 158 17 riscv-013.c:409 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 159 17 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 3i
Debug: 160 17 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 161 17 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 162 17 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 4i
Debug: 163 17 riscv-013.c:399 scan(): 41b r 00000000 @10 -> b 00000000 @10; 4i
Debug: 164 17 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=5, ac_busy_delay=0
Debug: 165 17 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 166 18 riscv-013.c:399 scan(): 41b r 00000000 @10 -> + 00000000 @10; 5i
Debug: 167 18 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 5i
Debug: 168 18 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=6, ac_busy_delay=0
Debug: 169 18 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 170 18 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 6i
Error: 171 18 riscv-013.c:1612 examine(): Debug Module did not become active. dmcontrol=0x0
Debug: 172 18 target.c:1825 target_call_event_callbacks(): target event 20 (examine-fail) for core riscv.cpu
Warn : 173 18 target.c:782 target_examine(): target riscv.cpu examination failed
Debug: 174 18 openocd.c:162 handle_init_command(): target examination failed
Debug: 175 18 command.c:146 script_debug(): command - flash init
Debug: 177 18 tcl.c:1385 handle_flash_init_command(): Initializing flash devices...
Debug: 178 18 command.c:146 script_debug(): command - nand init
Debug: 180 18 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 181 18 command.c:146 script_debug(): command - pld init
Debug: 183 18 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Info : 184 18 gdb_server.c:3503 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 185 18 server.c:311 add_service(): Listening on port 3333 for gdb connections
Debug: 186 18 command.c:146 script_debug(): command - halt
Debug: 188 18 target.c:3260 handle_halt_command(): -
Error: 189 18 target.c:579 target_halt(): Target not examined yet
Debug: 190 18 command.c:628 run_command(): Command 'halt' failed with error code -4
User : 191 18 command.c:694 command_run_line(): 
Debug: 192 18 riscv.c:472 riscv_deinit_target(): riscv_deinit_target()
Debug: 193 18 riscv-013.c:1530 deinit_target(): riscv_deinit_target()
Debug: 194 18 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas

openocd script:

# https://docs.xilinx.com/r/en-US/ug470_7Series_Config/Configuration-Bitstream-Lengths
# https://github.com/arduino/OpenOCD/blob/master/tcl/target/zynq_7000.cfg
# https://github.com/arduino/OpenOCD/blob/master/tcl/interface/ftdi/digilent-hs1.cfg
# https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md

# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

adapter driver ftdi
transport select jtag
ftdi_tdo_sample_edge falling
ftdi_device_desc "TUL"
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x0088 0x008b
reset_config none

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Configure JTAG expected ID
set _EXPECTED_ID 0x23727093

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version

# just to avoid a warning about the auto-detected arm core
# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

adapter speed 1000

riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard

reset_config none

init
halt

[TommyMurphyTM1234]

openocd version is 0.11.0

You should at least try a more recent build of OpenOCD. E.g. a build of the latest version from this repo. There have been a lot of changes since 0.11.0 and some of them may be relevant to your situation.

[newfrogg]

P/S: I still fail when using riscv-openocd 0.12.0+dev-03692-g3c88a95d4. Got the same error.

Hmm, I have updated some deprecated command, but this still fails. The new openocd script.

adapter driver ftdi
transport select jtag
ftdi tdo_sample_edge falling
ftdi device_desc "TUL"
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x0088 0x008b
reset_config none

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Configure JTAG expected ID
set _EXPECTED_ID 0x23727093

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version

# just to avoid a warning about the auto-detected arm core
# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

adapter speed 10000

# riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard

reset_config none

init
halt

[TommyMurphyTM1234]

In that case you'll probably need to use something like (ChipScope?) logic analysis probing of the relevant signals in the FPGA implementation in order to debug why the debug module isn't becoming active. And also check the sort of stuff that I mentioned here earlier:

• https://github.com/riscv-collab/riscv-openocd/issues/966#issuecomment-1836005846

[l1onog]

P/S: I still fail when using riscv-openocd 0.12.0+dev-03692-g3c88a95d4. Got the same error.

Hmm, I have updated some deprecated command, but this still fails. The new openocd script.

adapter driver ftdi
transport select jtag
ftdi tdo_sample_edge falling
ftdi device_desc "TUL"
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x0088 0x008b
reset_config none

# Configure JTAG chain and the target processor
set _CHIPNAME riscv

# Configure JTAG expected ID
set _EXPECTED_ID 0x23727093

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version

# just to avoid a warning about the auto-detected arm core
# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

adapter speed 10000

# riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard

reset_config none

init
halt

Hi @newfrogg, have you fixed that issue. I get the same problem as you. The dmcontrol=0x00 and debug module is not active. Some thing like below. If you fixed that issue, It would like to know your solution. Thank you.

[newfrogg]

Hi @l1onog, I don't know you are dealing with ibex-demo-system or not. For my case, adding the config udev device rule for Pynq Z2 is the solution. You could use my config as reference. Also, openocd cleaned & rebuilt from source is a good start. https://github.com/newfrogg/ibex-demo-system?tab=readme-ov-file#add-udev-rules-for-our-device.

[TommyMurphyTM1234]

Hi @l1onog, I don't know you are dealing with ibex-demo-system or not. For my case, adding the config udev device rule for Pynq Z2 is the solution. You could use my config as reference. Also, openocd cleaned & rebuilt from source is a good start. https://github.com/newfrogg/ibex-demo-system?tab=readme-ov-file#add-udev-rules-for-our-device.

I don't see any evidence that the issue mentioned above is related to, or would be solved by, udev rules installation. If it was then the test would not have worked at all unless root privileges were used e.g. via su/sudo in order to connect to and use the JTAG probe.