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riscv-collab / v8

Port of Google v8 engine to RISC-V.
https://github.com/v8-riscv/v8/wiki
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Remove code generation of "fmv.x.d" as well as "fmv.d.x" #592

Closed qjivy closed 2 years ago

qjivy commented 2 years ago

cmd line:

out/riscv32.debug/cctest test-assembler-riscv32/NAN_BOX --random-seed=-75565327 --nohard-abort --enable-slow-asserts --verify-heap --testing-d8-test-runner

error log:

Sim: Unsupported inst. Func:DecodeRVRFPType Line:4075 PC:0x30a44044 e2050553       fmv.x.d   a0, fa0            
Aborted