riscv-collab / v8

Port of Google v8 engine to RISC-V.
https://github.com/v8-riscv/v8/wiki
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TraceMemRd/Wr for double in simulator should be refactor #689

Closed qjivy closed 2 years ago

qjivy commented 2 years ago

In RV64, all values read-from-mem and write-to-mem can be viewed as 64bit because GPR and FPR are all 64bit wide. For lw/sw and flw/fsw, the simulator helper for this 4 instruction would handle the upper 32bit to a proper value.

However, for RV32, we should distinguish 32bit GPR rd/wr, 32bit FPR rd/wr and 64bit FPR rd/wr. We can no longer depend on the templated TraceMemRd and TraceMemWr function. Because the value reg_value int 64bit for fld/fsd.

Error would happen as following picture shows, the upper 32bit would be displayed as all zeros. This would bring misunderstanding when debugging.

qjivy commented 2 years ago

image