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riscv-mcu / GD32VF103_Firmware_Library

Original GD32VF103 Firmware Library
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performance counters are stopped(mcycle and mintret) #8

Open 123swk123 opened 4 years ago

123swk123 commented 4 years ago

CSR_MCOUNTINHIBIT is reset back to 0x05 after executing function libc_init_array https://github.com/riscv-mcu/GD32VF103_Firmware_Library/blob/12b61d1bf29afbee8ec4eee81cdbf1bd9f89470a/Firmware/RISCV/env_Eclipse/start.S#L237

even though it was cleared at https://github.com/riscv-mcu/GD32VF103_Firmware_Library/blob/12b61d1bf29afbee8ec4eee81cdbf1bd9f89470a/Firmware/RISCV/env_Eclipse/start.S#L233

clear these bits just before calling main.

fanghuaqi commented 3 years ago

Hi @123swk123,

We have improved the startup and exception handling for Nuclei RISC-V processor using NMSIS, and adjust the gd32vf103 firmware in our Nuclei SDK, which will of course fix the issue.

Thanks Huaqi

123swk123 commented 3 years ago

Has it been fixed already?

If so please share the commit details let me try to use it for my current work and feedback if I find something.

fanghuaqi commented 3 years ago

It is not fixed in this repo, it is fixed in a seperated repo mentioned above maintained by Nuclei RISC-V Processor software team.

Thanks Huaqi

fanghuaqi commented 3 years ago

If you are using this repo, you can simply change this csrci CSR_MCOUNTINHIBIT, 0x5 to csrsi CSR_MCOUNTINHIBIT, 0x5 to enable the cycle/instret counter.

Thanks Huaqi