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riscv-non-isa / iopmp-spec

This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
https://jira.riscv.org/browse/RVG-56
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Inconsistent names of global bus error suppression bit (bit 2 of ERR_CFG) #3

Closed tyshyu closed 1 month ago

tyshyu commented 5 months ago

Hi all,

I have read spec from the latest commits (https://github.com/riscv-non-isa/iopmp-spec/commit/3369da40e838a163c012c8775261d10a721c36d5 https://github.com/riscv-non-isa/iopmp-spec/commit/7a76c5d4c1c785c202ccbbd745910f01eea65055) and found inconsistent names about global bus error suppression bit (bit 2 of ERR_CFG).

The detail is on following descriptions:

Section 2.7 Error Reactions(chapter2.adoc):

  1. The IOPMP will signal the bus to the presence of a violation but will suppress the bus error if ERR_CFG.re is implemented and set to 1 on a violation.

  2. Regardless of the value on ERR_CFG.rre, IOPMP will indicate a "bus error suppression" when sere on an entry is set to 1.

Section 6.4 Error Capture Registers (chapter5.adoc):

  1. Name of bit 2 in ERRCFG is rs.

Section 6.7 Entry Array Registers (chapter5.adoc):

  1. Description of ENTRY_CFG(i).sere: 0x0: the response by ERR_CFG.rre.
  2. Description of ENTRY_CFG(i).sewe: 0x0: the response by ERR_CFG.rwe.
  3. Description of ENTRY_CFG(i).sexe: 0x0: the response by ERR_CFG.rxe.
channingt commented 5 months ago

Thanks and ack, will fix in next push.