Missing descriptions for HWCFG0.peis on Section 2.7 Error Reactions

riscv-non-isa / iopmp-spec

This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

https://jira.riscv.org/browse/RVG-56

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Missing descriptions for HWCFG0.peis on Section 2.7 Error Reactions #5

Closed tyshyu closed 1 month ago

tyshyu commented 5 months ago

Hi all,

The description "HWCFG0.peis is 1 if an implementation supports sire, siwe, or sixe." is in spec V0.9.1 but is removed from the latest commits (3369da4 7a76c5d).

HWCFG0.peis (IOPMP implements interrupt suppression per entry) is only mentioned in register description of HWCFG0 now.

It would be better if the description is in Section 2.7 like HWCFG0.pees (IOPMP implements the error suppression per entry).

channingt commented 5 months ago

Thanks for the suggestion. Added back the description, will be available on next release.