riscv-non-isa / riscv-ap-tee

This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
https://jira.riscv.org/browse/RVG-76
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Chapter 7.3.2 - EMTT with multiple TSMs #106

Open eckhard-delfs-qualcomm opened 1 week ago

eckhard-delfs-qualcomm commented 1 week ago

"For implementations that utilize MTT, the Extended Memory Tracking Table (EMTT) information managed by the TSM..."

In the scenario of multiple (confidential) TSMs, is the EMTT managed by the TSM driver, or should there be one EMTT per TSM instance? In the latter case, the information tracking involves checking multiple MTT instances.